Compact modelling of through-silicon vias (TSVs) in three-dimensional (3-D) integrated circuits.

Weerasekera, R., Grange, M., Pamunuwa, D. B., Tenhunen, H. & Zheng, L-R., 10/2009, Proceedings of the IEEE International Conference on 3D System Integration (3D IC), 2009. San Francisco: IEEE

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

Scalability of Network-on-Chip communication architecture for 3-D meshes.

Weldezion, A. Y., Grange, M., Pamunuwa, D. B., Lu, Z., Jantsch, A., Weerasekera, R. & Tenhunen, H., 12/06/2009, Proc. ACM/IEEE International Symposium on Networks on Chip (NOCS). San Diego: IEEE, p. 114-123 10 p.

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

Bandwidth optimization for through silicon via (TSV) bundles in 3D integrated circuits.

Weldezion, A., Weerasekera, R., Pamunuwa, D. B., Zheng, L-R. & Tenhunen, H., 2009, Workshop Notes, Design, Automation and Test in Europe (DATE). Nice

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

Closed-form equations for through-silicon via (TSV) parasitics in 3-D integrated circuits (ICs).

Weerasekera, R., Pamunuwa, D. B., Grange, M., Tenhunen, H. & Zheng, L-R., 2009, Workshop Notes, Design, Automation and Test in Europe (DATE). Nice

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

Design of robust molecular electronic circuits.

Lei, C., Pamunuwa, D. B., Bailey, S. & Lambert, C., 2009, IEEE International Symposium on Circuits and Systems, 2009. ISCAS 2009.. Taiwan: IEEE, p. 1819-1822 4 p.

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Conference contribution/Paper › peer-review

Designing reliable digital molecular electronic circuits.

Lei, C., Pamunuwa, D. B., Bailey, S. & Lambert, C., 2009, Nano-Net 4th International ICST Conference, Nano-Net 2009, Lucerne, Switzerland, October 18-20, 2009. Proceedings. Schmid, A., Goel, S., Wang, W., Beiu, V. & Carrara, S. (eds.). Berlin: Springer, p. 111-115 5 p. (Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering).

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Conference contribution/Paper › peer-review

Exploration of Through Silicon Via Interconnect Parasitics for 3-Dimensional Integrated Circuits

Grange, M., Weerasekera, R., Pamunuwa, D. & Tenhunen, H., 2009, Workshop Notes, Design, Automation and Test in Europe (DATE). Nice

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

Physical Mapping and Performance Study of a Multi-Clock 3-Dimensional Network-on-Chip Mesh.

Grange, M., Weldezion, A. Y., Pamunuwa, D. B., Weerasekera, R., Zhonghai, L., Jantsch, A. & Shippen, D., 2009, Proceedings of the IEEE International Conference on 3D System Integration (3D IC), 2009. San Francisco: IEEE

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

Application of molecular electronics devices in digital circuit design.

Lei, C., Pamunuwa, D. B., Bailey, S. & Lambert, C., 09/2008, Nano-Net Third International ICST Conference, NanoNet 2008, Boston, MA, USA, September 14-16, 2008, Revised Selected Papers. Cheng, M. (ed.). Berlin: Springer, p. 61-65 5 p. (Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering).

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Conference contribution/Paper › peer-review

Memory technology for extended large-scale integration in future electronics applications.

Pamunuwa, D. B., 03/2008, Proc. Design, Automation and Test in Europe (DATE) Conference. Munich: IEEE, p. 1126-1127 2 p.

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

Extending systems-on-chip to the third dimension : performance, cost and technological tradeoffs.

Weerasekera, R., Zheng, L-R., Pamunuwa, D. B. & Tenhunen, H., 11/2007, Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD). San Jose, California: IEEE, p. 212-219 8 p.

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

Early selection of system implementation choice among SoC, SoP and 3-D integration.

Weerasekera, R., Zheng, L-R., Pamunuwa, D. B. & Tenhunen, H., 09/2007, Proc. International System-On-Chip Conference (SOCC). Hsin Chu, Taiwan: IEEE

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

Molecular electronics device modeling for system design.

Lei, C., Pamunuwa, D. B., Bailey, S. & Lambert, C., 08/2007, Proc. IEEE International Conference on Nanotechnology. Hong Kong: IEEE, p. 1116-1119 4 p.

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

Delay-balanced smart repeaters for on-chip global signaling.

Weerasekera, R., Pamunuwa, D. B., Zheng, L-R. & Tenhunen, H., 12/02/2007, Proc. International Conference on VLSI Design. Bangalore: IEEE, p. 308-313 6 p.

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

Nanodevices : from novelty toys to functional devices - an integration perspective.

Pamunuwa, D. & Weerasekera, R., 08/2006, Proceedings of the IEEE international conference on industrial and information systems.. p. 103 -108

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

Minimal-power, delay-balanced smart repeaters for interconnects in the nanometer regime.

Weerasekera, R., Pamunuwa, D. B., Zheng, L-R. & Tenhunen, H., 03/2006, Proc. International Workshop on System-level Interconnect Prediction (SLIP). Munich: ACM, p. 113-120 8 p.

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

Switching sensitive driver circuit to combat dynamic delay in on-chip buses

Weerasekera, R., Zheng, L-R., Pamunuwa, D. B., Tenhunen, H., Paliouras, V. (ed.), Vounckx, J. (ed.) & Verkest, D. (ed.), 09/2005, Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005. Proceedings. Paliouras, V., Vounckx, J. & Verkest, D. (eds.). Berlin: Springer, p. 277-285 9 p. (Lecture Notes in Computer Science; vol. 3728).

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

Crosstalk immune interconnect driver design.

Weerasekera, R., Pamunuwa, D. B., Zheng, L. R. & Tenhunen, H., 2004, Proceedings of the international symposium on system-on-chip conference. p. 139-142 4 p.

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

A global wire planning scheme for Network-on-Chip.

Liu, J., Zheng, L-R., Pamunuwa, D. B. & Tenhunen, H., 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.. Vol. 4. p. IV-892-IV-895

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

Analytic modeling of interconnects for deep submicron circuits.

Pamunuwa, D. B., Elassaad, S. & Tenhunen, H., 2003, 2003 International Conference on Computer-Aided Design (ICCAD'03). San Jose, California: IEEE Computer Society, p. 835-842 8 p.

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

Closed form metrics to accurately model the response in general arbitrarily-coupled RC trees.

Pamunuwa, D. B. & Elassaad, S., 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.. IEEE, Vol. 4. p. IV-604

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

Layout, performance and power trade-offs in mesh-based network-on chip architectures.

Pamunuwa, D. B., Öberg, J., Zheng, L-R., Millberg, M., Jantsch, A. & Tenhunen, H., 2003, Proc. IFIP International Conference on VLSI Systems-on-chip. Darmstadt, Germany: Technische Universität Darmstadt, Insitute of Microelectronic Systems, p. 362-366 5 p.

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

On dynamic delay and repeater insertion in distributed capacitively coupled interconnects.

Pamunuwa, D. B. & Tenhunen, H., 2002, International Symposium on Quality Electronic Design, 2002. Proceedings.. IEEE, p. 240-245 6 p.

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

On dynamic delay and repeater insertion.

Tenhunen, H. & Pamunuwa, D. B., 2002, IEEE International Symposium on Circuits and Systems, 2002. IEEE, p. 97-100 4 p.

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

Optimising bandwidth over deep sub-micron interconnect.

Pamunuwa, D. B., Zheng, L-R. & Tenhunen, H., 2002, 2002 IEEE International Symposium on Circuits and Systems. IEEE, Vol. 4. p. IV-193

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

Repeater insertion to minimise delay in coupled interconnects.

Pamunuwa, D. B. & Tenhunen, H., 2001, Fourteenth International Conference on VLSI Design, 2001.. Bangalore, India: IEEE, p. 513-517 5 p.

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

Accurate a priori signal integrity estimation using a multilevel dynamic interconnect model for deep submicron VLSI design.

Zheng, L-R., Pamunuwa, D. B. & Tenhunen, H., 2000, Proceedings of the 26th European Solid-State Circuits Conference, 2000. ESSCIRC '00.. IEEE, p. 352-355 4 p.

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

Combating digital noise in high speed ULSI circuits using binary BCH encoding.

Pamunuwa, D. B., Zheng, L-R. & Tenhunen, H., 2000, The 2000 IEEE International Symposium on Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva.. Geneva: IEEE, Vol. 4. p. 13-16 4 p.

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

Error-control coding to combat digital noise in interconnects for ULSI circuits.

Pamunuwa, D. B., Zheng, L-R. & Tenhunen, H., 1999, Proc. IEEE Norchip Conference Oslo 1999. Norway: IEEE, p. 275-282 8 p.

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter