Supply Current Testing (IDDQ) has become an important defect oriented test
strategy for digital IC products. The technique takes advantage of the low
quiescent supply current drawn by static CMOS circuits relative to the
current consumption during state changes. However, in analogue and
mixed signal IC’s this condition can rarely be observed, as in most circuits,
steady state currents depend on the biasing conditions and the circuit
design.
This paper reviews analogue current monitoring proposals, investigates
some of the problems related to the use of these techniques and attempts to
categorise a number of analogue design styles against the probable
suitability for current testing methodologies.