The following paper describes how a well known adaptive error protection technique can be combined with synclxonisation on a single integrated circuit. The adaptive error protection is provided by the use of nested trellis decoders which allow soft decision maximum likelihood decoding. Synchronisation is provided by tlie Trellis Extracted Synchronisation Technique (TEST) method which can provide both symbol and block synchronisation. The combination of both these algorithms on a single chip suggests a low cost solution to problems of coding and synchronisation in a packet based protocol for powerline communications.