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A design-for-test structure for optimising analogue and mixed signal IC test

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A design-for-test structure for optimising analogue and mixed signal IC test. / Bratt, Adrian; Richardson, A. M. D.; Harvey, Russell et al.
European Design and Test Conference. IEEE, 1995. p. 24-33.

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

Harvard

Bratt, A, Richardson, AMD, Harvey, R & Dorey, AP 1995, A design-for-test structure for optimising analogue and mixed signal IC test. in European Design and Test Conference. IEEE, pp. 24-33. https://doi.org/10.1109/EDTC.1995.470424

APA

Bratt, A., Richardson, A. M. D., Harvey, R., & Dorey, A. P. (1995). A design-for-test structure for optimising analogue and mixed signal IC test. In European Design and Test Conference (pp. 24-33). IEEE. https://doi.org/10.1109/EDTC.1995.470424

Vancouver

Bratt A, Richardson AMD, Harvey R, Dorey AP. A design-for-test structure for optimising analogue and mixed signal IC test. In European Design and Test Conference. IEEE. 1995. p. 24-33 doi: 10.1109/EDTC.1995.470424

Author

Bratt, Adrian ; Richardson, A. M. D. ; Harvey, Russell et al. / A design-for-test structure for optimising analogue and mixed signal IC test. European Design and Test Conference. IEEE, 1995. pp. 24-33

Bibtex

@inbook{175a99204b8c4e5a8f0cd5176ea57e22,
title = "A design-for-test structure for optimising analogue and mixed signal IC test",
abstract = "A new Design-for-Test (DfT) structure based on a configurable operational amplifier, referred to as a “swap amp” is presented that allows access to embedded analogue blocks. The structure has minimal impact on circuit performance and has been evaluated on a custom designed Phase Locked Loop (PLL) structure. A test chip containing faulty and fault free versions of this PLL structure, with and without DfT modifications, has been fabricated and an evaluation of this DfT scheme based on the swap-amp structure carried out. It is shown that for embedded analogue blocks, the DfT strategy can not only improve and simplify analogue and mixed signal IC test, but can also be used for diagnostics.",
author = "Adrian Bratt and Richardson, {A. M. D.} and Russell Harvey and Dorey, {A. P.}",
note = "{"}{\textcopyright}1995 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.{"} {"}This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.{"}",
year = "1995",
month = mar,
doi = "10.1109/EDTC.1995.470424",
language = "English",
pages = "24--33",
booktitle = "European Design and Test Conference",
publisher = "IEEE",

}

RIS

TY - CHAP

T1 - A design-for-test structure for optimising analogue and mixed signal IC test

AU - Bratt, Adrian

AU - Richardson, A. M. D.

AU - Harvey, Russell

AU - Dorey, A. P.

N1 - "©1995 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE." "This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder."

PY - 1995/3

Y1 - 1995/3

N2 - A new Design-for-Test (DfT) structure based on a configurable operational amplifier, referred to as a “swap amp” is presented that allows access to embedded analogue blocks. The structure has minimal impact on circuit performance and has been evaluated on a custom designed Phase Locked Loop (PLL) structure. A test chip containing faulty and fault free versions of this PLL structure, with and without DfT modifications, has been fabricated and an evaluation of this DfT scheme based on the swap-amp structure carried out. It is shown that for embedded analogue blocks, the DfT strategy can not only improve and simplify analogue and mixed signal IC test, but can also be used for diagnostics.

AB - A new Design-for-Test (DfT) structure based on a configurable operational amplifier, referred to as a “swap amp” is presented that allows access to embedded analogue blocks. The structure has minimal impact on circuit performance and has been evaluated on a custom designed Phase Locked Loop (PLL) structure. A test chip containing faulty and fault free versions of this PLL structure, with and without DfT modifications, has been fabricated and an evaluation of this DfT scheme based on the swap-amp structure carried out. It is shown that for embedded analogue blocks, the DfT strategy can not only improve and simplify analogue and mixed signal IC test, but can also be used for diagnostics.

U2 - 10.1109/EDTC.1995.470424

DO - 10.1109/EDTC.1995.470424

M3 - Chapter

SP - 24

EP - 33

BT - European Design and Test Conference

PB - IEEE

ER -