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A digital partial built-in self-test structure for a high performance automatic gain control circuit

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Publication date1999
Host publicationDESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION 1999, PROCEEDINGS
EditorsD Borrione, R Ernst
Place of PublicationLOS ALAMITOS
PublisherIEEE COMPUTER SOC
Pages232-238
Number of pages7
ISBN (Print)0-7695-0078-1
<mark>Original language</mark>English

Abstract

It is now widely recognised that Design-for-Testability and Built-in Self-Test techniques rc ill be mandatory to meet test and quality specifications in next generation mired signal integrated systems. This paper describes a new digital on-chip post processing function capable of reducing production test time for a high performance automatic gain control circuit by 70%.