Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter
Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter
}
TY - CHAP
T1 - A fault simulation methodology for MEMS.
AU - Rosing, R.
AU - Richardson, A. M. D.
AU - Dorey, A. P.
N1 - ©2000 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE." "This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.
PY - 2000
Y1 - 2000
N2 - Efficient built-in and external test strategies are becoming essential in microelectromechanical systems (MEMS), especially for high reliability and safety critical applications. To be realistic however, internal and external test must be properly validated in terms of fault coverage. Fault simulation is hence likely to become a critical utility within the design flow. This paper discuss methods for achieving test support based on the extension of tools and techniques currently being introduced into the mixed signal ASIC market.
AB - Efficient built-in and external test strategies are becoming essential in microelectromechanical systems (MEMS), especially for high reliability and safety critical applications. To be realistic however, internal and external test must be properly validated in terms of fault coverage. Fault simulation is hence likely to become a critical utility within the design flow. This paper discuss methods for achieving test support based on the extension of tools and techniques currently being introduced into the mixed signal ASIC market.
U2 - 10.1109/DATE.2000.840828
DO - 10.1109/DATE.2000.840828
M3 - Chapter
SN - 0-7695-0537-6.
SP - 476
EP - 483
BT - Proceedings of the design automation and test in Europe conference
PB - IEEE
CY - Paris
ER -