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Adaptive Optimization of Sparse Matrix-Vector Multiplication on Emerging Many-Core Architectures

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSNConference contribution/Paper

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Adaptive Optimization of Sparse Matrix-Vector Multiplication on Emerging Many-Core Architectures. / Chen, Shizhao; Fang, Jianbin; Chen, Donglin; Xu, Chuanfu; Wang, Zheng.

The 20th IEEE International Conference on High Performance Computing and Communications (HPCC) . IEEE, 2018. p. 649-658.

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSNConference contribution/Paper

Harvard

Chen, S, Fang, J, Chen, D, Xu, C & Wang, Z 2018, Adaptive Optimization of Sparse Matrix-Vector Multiplication on Emerging Many-Core Architectures. in The 20th IEEE International Conference on High Performance Computing and Communications (HPCC) . IEEE, pp. 649-658. https://doi.org/10.1109/HPCC/SmartCity/DSS.2018.00116

APA

Chen, S., Fang, J., Chen, D., Xu, C., & Wang, Z. (2018). Adaptive Optimization of Sparse Matrix-Vector Multiplication on Emerging Many-Core Architectures. In The 20th IEEE International Conference on High Performance Computing and Communications (HPCC) (pp. 649-658). IEEE. https://doi.org/10.1109/HPCC/SmartCity/DSS.2018.00116

Vancouver

Chen S, Fang J, Chen D, Xu C, Wang Z. Adaptive Optimization of Sparse Matrix-Vector Multiplication on Emerging Many-Core Architectures. In The 20th IEEE International Conference on High Performance Computing and Communications (HPCC) . IEEE. 2018. p. 649-658 https://doi.org/10.1109/HPCC/SmartCity/DSS.2018.00116

Author

Chen, Shizhao ; Fang, Jianbin ; Chen, Donglin ; Xu, Chuanfu ; Wang, Zheng. / Adaptive Optimization of Sparse Matrix-Vector Multiplication on Emerging Many-Core Architectures. The 20th IEEE International Conference on High Performance Computing and Communications (HPCC) . IEEE, 2018. pp. 649-658

Bibtex

@inproceedings{af69943eb9cb4a4886df088fd1e0f836,
title = "Adaptive Optimization of Sparse Matrix-Vector Multiplication on Emerging Many-Core Architectures",
abstract = "Sparse matrix vector multiplication (SpMV) is one of the most common operations in scientific and high-performance applications, and is often responsible for the application performance bottleneck. While the sparse matrix representation has a significant impact on the resulting application performance, choosing the right representation typically relies on expert knowledge and trial and error. This paper provides the first comprehensive study on the impact of sparse matrix representations on two emerging many-core architectures: the Intel's Knights Landing (KNL) XeonPhi and the ARM-based FT-2000Plus (FTP). Our large-scale experiments involved over 9,500 distinct profiling runs performed on 956 sparse datasets and five mainstream SpMV representations. We show that the best sparse matrix representation depends on the underlying architecture and the program input. To help developers to choose the optimal matrix representation, we employ machine learning to develop a predictive model. Our model is first trained offline using a set of training examples. The learned model can be used to predict the best matrix representation for any unseen input for a given architecture. We show that our model delivers on average 95% and 91% of the best available performance on KNL and FTP respectively, and it achieves this with no runtime profiling overhead.",
author = "Shizhao Chen and Jianbin Fang and Donglin Chen and Chuanfu Xu and Zheng Wang",
note = "{\textcopyright}2018 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.",
year = "2018",
month = jun,
day = "28",
doi = "10.1109/HPCC/SmartCity/DSS.2018.00116",
language = "English",
pages = "649--658",
booktitle = "The 20th IEEE International Conference on High Performance Computing and Communications (HPCC)",
publisher = "IEEE",

}

RIS

TY - GEN

T1 - Adaptive Optimization of Sparse Matrix-Vector Multiplication on Emerging Many-Core Architectures

AU - Chen, Shizhao

AU - Fang, Jianbin

AU - Chen, Donglin

AU - Xu, Chuanfu

AU - Wang, Zheng

N1 - ©2018 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.

PY - 2018/6/28

Y1 - 2018/6/28

N2 - Sparse matrix vector multiplication (SpMV) is one of the most common operations in scientific and high-performance applications, and is often responsible for the application performance bottleneck. While the sparse matrix representation has a significant impact on the resulting application performance, choosing the right representation typically relies on expert knowledge and trial and error. This paper provides the first comprehensive study on the impact of sparse matrix representations on two emerging many-core architectures: the Intel's Knights Landing (KNL) XeonPhi and the ARM-based FT-2000Plus (FTP). Our large-scale experiments involved over 9,500 distinct profiling runs performed on 956 sparse datasets and five mainstream SpMV representations. We show that the best sparse matrix representation depends on the underlying architecture and the program input. To help developers to choose the optimal matrix representation, we employ machine learning to develop a predictive model. Our model is first trained offline using a set of training examples. The learned model can be used to predict the best matrix representation for any unseen input for a given architecture. We show that our model delivers on average 95% and 91% of the best available performance on KNL and FTP respectively, and it achieves this with no runtime profiling overhead.

AB - Sparse matrix vector multiplication (SpMV) is one of the most common operations in scientific and high-performance applications, and is often responsible for the application performance bottleneck. While the sparse matrix representation has a significant impact on the resulting application performance, choosing the right representation typically relies on expert knowledge and trial and error. This paper provides the first comprehensive study on the impact of sparse matrix representations on two emerging many-core architectures: the Intel's Knights Landing (KNL) XeonPhi and the ARM-based FT-2000Plus (FTP). Our large-scale experiments involved over 9,500 distinct profiling runs performed on 956 sparse datasets and five mainstream SpMV representations. We show that the best sparse matrix representation depends on the underlying architecture and the program input. To help developers to choose the optimal matrix representation, we employ machine learning to develop a predictive model. Our model is first trained offline using a set of training examples. The learned model can be used to predict the best matrix representation for any unseen input for a given architecture. We show that our model delivers on average 95% and 91% of the best available performance on KNL and FTP respectively, and it achieves this with no runtime profiling overhead.

U2 - 10.1109/HPCC/SmartCity/DSS.2018.00116

DO - 10.1109/HPCC/SmartCity/DSS.2018.00116

M3 - Conference contribution/Paper

SP - 649

EP - 658

BT - The 20th IEEE International Conference on High Performance Computing and Communications (HPCC)

PB - IEEE

ER -