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An approach to realistic fault prediction and layout design for testability in analog circuits

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Publication date1998
Host publicationDesign, Automation and Test in Europe, 1998 Proceedings
Place of publicationLOS ALAMITOS
PublisherIEEE COMPUTER SOC
Pages905-909
Number of pages5
ISBN (Print)0-8186-8359-7
Original languageEnglish

Abstract

This paper presents an approach towards realistic fault prediction in analog circuits. It exploits the Inductive Fault Analysis (IFA) methodology to generate explicit models able to give the probability of occurrence of faults associated with devices in an analog cell. This information intends to facilitate the integration of design and test phases in the development of an IC since it provides a realistic fault list for simulation before going to the final layout, and also makes possible layout optimization towards what we can call layout level design for testability.