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An approach to realistic fault prediction and layout design for testability in analog circuits

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An approach to realistic fault prediction and layout design for testability in analog circuits. / Prieto, J A ; Rueda, A ; Grout, I et al.
Design, Automation and Test in Europe, 1998 Proceedings. LOS ALAMITOS: IEEE COMPUTER SOC, 1998. p. 905-909.

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Conference contribution/Paper › peer-review

Harvard

Prieto, JA, Rueda, A, Grout, I, Peralias, E, Huertas, JL & Richardson, AMD 1998, An approach to realistic fault prediction and layout design for testability in analog circuits. in Design, Automation and Test in Europe, 1998 Proceedings. IEEE COMPUTER SOC, LOS ALAMITOS, pp. 905-909. https://doi.org/10.1109/DATE.1998.655965

APA

Prieto, J. A., Rueda, A., Grout, I., Peralias, E., Huertas, J. L., & Richardson, A. M. D. (1998). An approach to realistic fault prediction and layout design for testability in analog circuits. In Design, Automation and Test in Europe, 1998 Proceedings (pp. 905-909). IEEE COMPUTER SOC. https://doi.org/10.1109/DATE.1998.655965

Vancouver

Prieto JA, Rueda A, Grout I, Peralias E, Huertas JL, Richardson AMD. An approach to realistic fault prediction and layout design for testability in analog circuits. In Design, Automation and Test in Europe, 1998 Proceedings. LOS ALAMITOS: IEEE COMPUTER SOC. 1998. p. 905-909 doi: 10.1109/DATE.1998.655965

Author

Prieto, J A ; Rueda, A ; Grout, I et al. / An approach to realistic fault prediction and layout design for testability in analog circuits. Design, Automation and Test in Europe, 1998 Proceedings. LOS ALAMITOS : IEEE COMPUTER SOC, 1998. pp. 905-909

Bibtex

@inproceedings{82664aaba0af4fa682259651c416e082,
title = "An approach to realistic fault prediction and layout design for testability in analog circuits",
abstract = "This paper presents an approach towards realistic fault prediction in analog circuits. It exploits the Inductive Fault Analysis (IFA) methodology to generate explicit models able to give the probability of occurrence of faults associated with devices in an analog cell. This information intends to facilitate the integration of design and test phases in the development of an IC since it provides a realistic fault list for simulation before going to the final layout, and also makes possible layout optimization towards what we can call layout level design for testability.",
author = "Prieto, {J A} and A Rueda and I Grout and E Peralias and Huertas, {J L} and Richardson, {A M D}",
year = "1998",
doi = "10.1109/DATE.1998.655965",
language = "English",
isbn = "0-8186-8359-7",
pages = "905--909",
booktitle = "Design, Automation and Test in Europe, 1998 Proceedings",
publisher = "IEEE COMPUTER SOC",

}

RIS

TY - GEN

T1 - An approach to realistic fault prediction and layout design for testability in analog circuits

AU - Prieto, J A

AU - Rueda, A

AU - Grout, I

AU - Peralias, E

AU - Huertas, J L

AU - Richardson, A M D

PY - 1998

Y1 - 1998

N2 - This paper presents an approach towards realistic fault prediction in analog circuits. It exploits the Inductive Fault Analysis (IFA) methodology to generate explicit models able to give the probability of occurrence of faults associated with devices in an analog cell. This information intends to facilitate the integration of design and test phases in the development of an IC since it provides a realistic fault list for simulation before going to the final layout, and also makes possible layout optimization towards what we can call layout level design for testability.

AB - This paper presents an approach towards realistic fault prediction in analog circuits. It exploits the Inductive Fault Analysis (IFA) methodology to generate explicit models able to give the probability of occurrence of faults associated with devices in an analog cell. This information intends to facilitate the integration of design and test phases in the development of an IC since it provides a realistic fault list for simulation before going to the final layout, and also makes possible layout optimization towards what we can call layout level design for testability.

U2 - 10.1109/DATE.1998.655965

DO - 10.1109/DATE.1998.655965

M3 - Conference contribution/Paper

SN - 0-8186-8359-7

SP - 905

EP - 909

BT - Design, Automation and Test in Europe, 1998 Proceedings

PB - IEEE COMPUTER SOC

CY - LOS ALAMITOS

ER -