The advent of enabling technologies for reconfigurable logic processing requires that investigation into new design methodologies is made before they can be used effectively. This paper presents the design of an FPGA configuration for the decoding of convolutional codes. These codes provide resilience in noisy transmission conditions for many different digital communication systems. The decoder can be reconfigured to decode any convolutional code up to constraint length 9 and any rate to a minimum of 1/6. This investigative design reveals methods on how to implement parametable algorithms using configurable logic.