Research output: Contribution in Book/Report/Proceedings › Conference contribution
|Host publication||IDDQ Testing, 1997. Digest of Papers., IEEE International Workshop on|
|Editors||AP Jayasumana, C Tong|
|Place of Publication||LOS ALAMITOS|
|Publisher||I E E E, COMPUTER SOC PRESS|
|Number of pages||5|
The success of I-ddq testing for digital circuits has motivated several groups to investigate if the same or a similar method could be applied to analogue domain. The diverse behavior of analogue circuits regarding quiescent current and the problem of global variations in nominal values are serious handicaps in obtaining a generic current-mode test method to be applied off chip. A promising test procedure is the built-in self-testing (BIST) technique for which circuits with class A behavior are specially suited. This paper focuses on these type of circuits and in particular those based on symmetric OTAs. Two BIST techniques that permit low silicon area overheads, low voltage operation, and negligible influence on the circuit performance are proposed and discussed. Hspice simulations from a 5th order OTA-C elliptic filler show that global fault coverages of 92.2% and 96.6% are achieved by the two techniques.