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Current-mode techniques for self-testing analogue circuits

Research output: Contribution in Book/Report/ProceedingsConference contribution

Published

Publication date1997
Host publicationIDDQ Testing, 1997. Digest of Papers., IEEE International Workshop on
EditorsAP Jayasumana, C Tong
Place of publicationLOS ALAMITOS
PublisherI E E E, COMPUTER SOC PRESS
Pages33-37
Number of pages5
ISBN (Print)0-8186-8123-3
Original languageEnglish

Abstract

The success of I-ddq testing for digital circuits has motivated several groups to investigate if the same or a similar method could be applied to analogue domain. The diverse behavior of analogue circuits regarding quiescent current and the problem of global variations in nominal values are serious handicaps in obtaining a generic current-mode test method to be applied off chip. A promising test procedure is the built-in self-testing (BIST) technique for which circuits with class A behavior are specially suited. This paper focuses on these type of circuits and in particular those based on symmetric OTAs. Two BIST techniques that permit low silicon area overheads, low voltage operation, and negligible influence on the circuit performance are proposed and discussed. Hspice simulations from a 5th order OTA-C elliptic filler show that global fault coverages of 92.2% and 96.6% are achieved by the two techniques.