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Current-mode techniques for self-testing analogue circuits

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Current-mode techniques for self-testing analogue circuits. / Baturone, I ; SanchezSolano, S ; Richardson, A M et al.
IDDQ Testing, 1997. Digest of Papers., IEEE International Workshop on . ed. / AP Jayasumana; C Tong. LOS ALAMITOS: I E E E, COMPUTER SOC PRESS, 1997. p. 33-37.

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Conference contribution/Paper › peer-review

Harvard

Baturone, I, SanchezSolano, S, Richardson, AM & Huertas, JL 1997, Current-mode techniques for self-testing analogue circuits. in AP Jayasumana & C Tong (eds), IDDQ Testing, 1997. Digest of Papers., IEEE International Workshop on . I E E E, COMPUTER SOC PRESS, LOS ALAMITOS, pp. 33-37. https://doi.org/10.1109/IDDQ.1997.633010

APA

Baturone, I., SanchezSolano, S., Richardson, A. M., & Huertas, J. L. (1997). Current-mode techniques for self-testing analogue circuits. In AP. Jayasumana, & C. Tong (Eds.), IDDQ Testing, 1997. Digest of Papers., IEEE International Workshop on (pp. 33-37). I E E E, COMPUTER SOC PRESS. https://doi.org/10.1109/IDDQ.1997.633010

Vancouver

Baturone I, SanchezSolano S, Richardson AM, Huertas JL. Current-mode techniques for self-testing analogue circuits. In Jayasumana AP, Tong C, editors, IDDQ Testing, 1997. Digest of Papers., IEEE International Workshop on . LOS ALAMITOS: I E E E, COMPUTER SOC PRESS. 1997. p. 33-37 doi: 10.1109/IDDQ.1997.633010

Author

Baturone, I ; SanchezSolano, S ; Richardson, A M et al. / Current-mode techniques for self-testing analogue circuits. IDDQ Testing, 1997. Digest of Papers., IEEE International Workshop on . editor / AP Jayasumana ; C Tong. LOS ALAMITOS : I E E E, COMPUTER SOC PRESS, 1997. pp. 33-37

Bibtex

@inproceedings{d7d90214e4b34ecc92ff512685f17e5f,
title = "Current-mode techniques for self-testing analogue circuits",
abstract = "The success of I-ddq testing for digital circuits has motivated several groups to investigate if the same or a similar method could be applied to analogue domain. The diverse behavior of analogue circuits regarding quiescent current and the problem of global variations in nominal values are serious handicaps in obtaining a generic current-mode test method to be applied off chip. A promising test procedure is the built-in self-testing (BIST) technique for which circuits with class A behavior are specially suited. This paper focuses on these type of circuits and in particular those based on symmetric OTAs. Two BIST techniques that permit low silicon area overheads, low voltage operation, and negligible influence on the circuit performance are proposed and discussed. Hspice simulations from a 5th order OTA-C elliptic filler show that global fault coverages of 92.2% and 96.6% are achieved by the two techniques.",
author = "I Baturone and S SanchezSolano and Richardson, {A M} and Huertas, {J L}",
year = "1997",
doi = "10.1109/IDDQ.1997.633010",
language = "English",
isbn = "0-8186-8123-3",
pages = "33--37",
editor = "AP Jayasumana and C Tong",
booktitle = "IDDQ Testing, 1997. Digest of Papers., IEEE International Workshop on",
publisher = "I E E E, COMPUTER SOC PRESS",

}

RIS

TY - GEN

T1 - Current-mode techniques for self-testing analogue circuits

AU - Baturone, I

AU - SanchezSolano, S

AU - Richardson, A M

AU - Huertas, J L

PY - 1997

Y1 - 1997

N2 - The success of I-ddq testing for digital circuits has motivated several groups to investigate if the same or a similar method could be applied to analogue domain. The diverse behavior of analogue circuits regarding quiescent current and the problem of global variations in nominal values are serious handicaps in obtaining a generic current-mode test method to be applied off chip. A promising test procedure is the built-in self-testing (BIST) technique for which circuits with class A behavior are specially suited. This paper focuses on these type of circuits and in particular those based on symmetric OTAs. Two BIST techniques that permit low silicon area overheads, low voltage operation, and negligible influence on the circuit performance are proposed and discussed. Hspice simulations from a 5th order OTA-C elliptic filler show that global fault coverages of 92.2% and 96.6% are achieved by the two techniques.

AB - The success of I-ddq testing for digital circuits has motivated several groups to investigate if the same or a similar method could be applied to analogue domain. The diverse behavior of analogue circuits regarding quiescent current and the problem of global variations in nominal values are serious handicaps in obtaining a generic current-mode test method to be applied off chip. A promising test procedure is the built-in self-testing (BIST) technique for which circuits with class A behavior are specially suited. This paper focuses on these type of circuits and in particular those based on symmetric OTAs. Two BIST techniques that permit low silicon area overheads, low voltage operation, and negligible influence on the circuit performance are proposed and discussed. Hspice simulations from a 5th order OTA-C elliptic filler show that global fault coverages of 92.2% and 96.6% are achieved by the two techniques.

U2 - 10.1109/IDDQ.1997.633010

DO - 10.1109/IDDQ.1997.633010

M3 - Conference contribution/Paper

SN - 0-8186-8123-3

SP - 33

EP - 37

BT - IDDQ Testing, 1997. Digest of Papers., IEEE International Workshop on

A2 - Jayasumana, AP

A2 - Tong, C

PB - I E E E, COMPUTER SOC PRESS

CY - LOS ALAMITOS

ER -