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Integration of graphene oxide buffer layer/graphene floating gate for wide memory window in Pt/Ti/Al2O3/GO/graphene/SiO2/p-Si/Au non-volatile (FLASH) applications

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<mark>Journal publication date</mark>18/06/2018
<mark>Journal</mark>Applied Physics Letters
Issue number25
Volume112
Number of pages5
Publication statusPublished
Original languageEnglish

Abstract

The excellent electronic properties of graphene such as high density of states, work-function, and low dimensionality promote the usage of graphene as an efficient floating gate (FG) layer for downscaled, high density non-volatile flash memories (NVFMs). However, the chemical inertness of graphene requires a buffer layer for the uniform deposition of a high-k blocking layer (high-k blocking oxide/buffer layer/graphene/SiO2/p-Si/Au). Herein, FG-NVFM devices are fabricated using few-layer graphene as a FG followed by deposition of spin-coated monolayer graphene oxide (GO) as a buffer layer. The simple, stress free deposition of GO decorated with the functional groups is anticipated for the uniform deposition of blocking oxide (Aluminum oxide, Al2O3) over GO/graphene/SiO2/p-Si/Au. Beyond this, it improves the interface (Al2O3/GO/graphene), leading to enhanced memory characteristics for the fabricated Pt/Ti/Al2O3/GO/graphene/SiO2/p-Si/Au FG-NVFM structure. The electrical characterizations of the fabricated FG-NVFM devices show a significantly wide memory window of ∼4.3 V @ ±7 V at 1 MHz and robust retention up to ∼2 × 1013 s (>15 years). These observations clearly reveal an efficient potential of graphene for FG and GO as a buffer layer for the future NVFM device applications. The authors thank the C4DFED and AMRC, IIT Mandi, for the graphene growth and electrical and material characterization facilities. The authors are also thankful to CeNSE, IISC Bangalore, (under INUP) for the deposition of tunnel and blocking layers and etching facilities for the fabrication of device structures. M.S. also thanks IIT Mandi for the financial support.