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Investigations for minimum invasion digital only built in ‘ramp’ based test techniques for charge pump PLLs.

Research output: Contribution in Book/Report/ProceedingsChapter

Published

Publication date2002
Host publicationProceedings of the Seventh IEEE European Test Workshop, 2002.
PublisherIEEE
Pages95-102
Number of pages8
ISBN (Print)0-7695-1715-3
Original languageEnglish

Abstract

Due to a number of desirable operational and design characteristics, CP-PLL's (Charge Pump Phase Locked Loops) have, in recent years become a pervasive PLL architecture. CP-PLL architectures are exploited for a variety of applications such as on chip clock generation, CRC (clock recovery circuits) and radio frequency synthesis applications. This paper describes a simple, digital only, minimally invasive and fully automated test approach for high performance CP-PLL's that can be used to provide more information about the CP-PLL function beyond that obtained through the commonly used FLT (Frequency Lock Test). The test strategy described here allows the estimation of forward path gain and relative leakage in the forward path loop components. Applications of the test are focussed towards digital only testing of fully embedded CP-PLL's, however further test modifications could yield marked test time improvements for embedded and board level CP-PLL's incorporating multiple CP currents and or multiple loop filter configurations.

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