TY - CHAP

T1 - Investigations for minimum invasion digital only built in ‘ramp’ based test techniques for charge pump PLLs.

AU - Burbidge, Martin J.

AU - Tijou, Jim

AU - Poullet, Frederic

AU - Richardson, Andrew M. D.

N1 - "©2002 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE." "This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder."

PY - 2002

Y1 - 2002

N2 - Due to a number of desirable operational and design characteristics, CP-PLL's (Charge Pump Phase Locked Loops) have, in recent years become a pervasive PLL architecture. CP-PLL architectures are exploited for a variety of applications such as on chip clock generation, CRC (clock recovery circuits) and radio frequency synthesis applications. This paper describes a simple, digital only, minimally invasive and fully automated test approach for high performance CP-PLL's that can be used to provide more information about the CP-PLL function beyond that obtained through the commonly used FLT (Frequency Lock Test). The test strategy described here allows the estimation of forward path gain and relative leakage in the forward path loop components. Applications of the test are focussed towards digital only testing of fully embedded CP-PLL's, however further test modifications could yield marked test time improvements for embedded and board level CP-PLL's incorporating multiple CP currents and or multiple loop filter configurations.

AB - Due to a number of desirable operational and design characteristics, CP-PLL's (Charge Pump Phase Locked Loops) have, in recent years become a pervasive PLL architecture. CP-PLL architectures are exploited for a variety of applications such as on chip clock generation, CRC (clock recovery circuits) and radio frequency synthesis applications. This paper describes a simple, digital only, minimally invasive and fully automated test approach for high performance CP-PLL's that can be used to provide more information about the CP-PLL function beyond that obtained through the commonly used FLT (Frequency Lock Test). The test strategy described here allows the estimation of forward path gain and relative leakage in the forward path loop components. Applications of the test are focussed towards digital only testing of fully embedded CP-PLL's, however further test modifications could yield marked test time improvements for embedded and board level CP-PLL's incorporating multiple CP currents and or multiple loop filter configurations.

U2 - 10.1109/ETW.2002.1029645

DO - 10.1109/ETW.2002.1029645

M3 - Chapter

SN - 0-7695-1715-3

SP - 95

EP - 102

BT - Proceedings of the Seventh IEEE European Test Workshop, 2002.

PB - IEEE

ER -