Phase locked loops are used in a variety of applications, including on chip clock synthesis, bit and symbol timing recovery for serial data streams, and generation of frequency agile high frequency carriers in FDMA communications products. In many applications the transient response of the PLL when it is subjected to a step change in input frequency is of paramount importance. Key parameters that describe the transient response and ultimately reflect the likely steady state response of a PLL are the damping factor, the natural frequency, the peak overshoot, the frequency settling, time, and phase settling time. In consequence many PLL designers subject their design simulations and completed designs to step response tests, whereby a step frequency change is applied to the PLL and the output response of the PLL is measured. This is a commonly used technique and the input stimuli are either applied directly to the PLL input, or alternatively the feedback divider is toggled between N and N+1. The output response is monitored either directly at the loop filter node (for chipset applications) or at the PLL output (for embedded applications). This paper presents ideas and techniques to enable the transient response of a fully embedded PLL to be automatically monitored using purely digital circuitry. To allow realisation of a BIST solution suggestions are made for comparing of the output response to response limits on chip.