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System in Package Technology - Design for Manufacture Challenges.

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System in Package Technology - Design for Manufacture Challenges. / Richardson, Andrew M. D.; Bailey, Chris; Dumas, Norbert et al.
In: Circuit World, Vol. 33, No. 1, 01.02.2007, p. 36-46.

Research output: Contribution to Journal/MagazineJournal articlepeer-review

Harvard

Richardson, AMD, Bailey, C, Dumas, N & Yannou, JM 2007, 'System in Package Technology - Design for Manufacture Challenges.', Circuit World, vol. 33, no. 1, pp. 36-46. https://doi.org/10.1108/03056120710723706

APA

Vancouver

Richardson AMD, Bailey C, Dumas N, Yannou JM. System in Package Technology - Design for Manufacture Challenges. Circuit World. 2007 Feb 1;33(1):36-46. doi: 10.1108/03056120710723706

Author

Richardson, Andrew M. D. ; Bailey, Chris ; Dumas, Norbert et al. / System in Package Technology - Design for Manufacture Challenges. In: Circuit World. 2007 ; Vol. 33, No. 1. pp. 36-46.

Bibtex

@article{85c448da1cb746cab1979272ac156cae,
title = "System in Package Technology - Design for Manufacture Challenges.",
abstract = "Purpose – To present key challenges associated with the evolution of system-in-package technologies and present technical work in reliability modeling and embedded test that contributes to these challenges. Design/methodology/approach – Key challenges have been identified from the electronics and integrated MEMS industrial sectors. Solutions to optimising the reliability of a typical assembly process and reducing the cost of production test have been studied through simulation and modelling studies based on technology data released by NXP and in collaboration with EDA tool vendors Coventor and Flomerics. Findings – Characterised models that deliver special and material dependent reliability data that can be used to optimize robustness of SiP assemblies together with results that indicate relative contributions of various structural variables. An initial analytical model for solder ball reliability and a solution for embedding a low cost test for a capacitive RF-MEMS switch identified as an SiP component presenting a key test challenge. Research limitations/implications – Results will contribute to the further development of NXP wafer level system-in-package technology. Limitations are that feedback on the implementation of recommendations and the physical characterisation of the embedded test solution. Originality/value – Both the methodology and associated studies on the structural reliability of an industrial SiP technology are unique. The analytical model for solder ball life is new as is the embedded test solution for the RF-MEMS switch.",
keywords = "Circuits, Electromechanical devices, Electronics industry, Reliability management",
author = "Richardson, {Andrew M. D.} and Chris Bailey and Norbert Dumas and Yannou, {Jean Marc}",
note = "A compilation of results from a collaboration between my team, the University of Greenwich and NXP, Caen under the EPSRC IeMRC project {"}{"}Design for Manufacture Methodology for SiP{"}{"}. The results obtained on structural reliability analysis in collaboration with the University of Greenwich are being used within NXP Semiconductors (ref. jean-marc.yannou@nxp.com) and the study on an embedded test solution for the RF-MEMS component formed the basis for a new IeMRC project with NXP and others. The work is to our knowledge the first peer reviewed article addressing solder ball reliability and embedded test on this type of SiP platform. RAE_import_type : Journal article RAE_uoa_type : General Engineering",
year = "2007",
month = feb,
day = "1",
doi = "10.1108/03056120710723706",
language = "English",
volume = "33",
pages = "36--46",
journal = "Circuit World",
publisher = "Emerald Group Publishing Ltd.",
number = "1",

}

RIS

TY - JOUR

T1 - System in Package Technology - Design for Manufacture Challenges.

AU - Richardson, Andrew M. D.

AU - Bailey, Chris

AU - Dumas, Norbert

AU - Yannou, Jean Marc

N1 - A compilation of results from a collaboration between my team, the University of Greenwich and NXP, Caen under the EPSRC IeMRC project ""Design for Manufacture Methodology for SiP"". The results obtained on structural reliability analysis in collaboration with the University of Greenwich are being used within NXP Semiconductors (ref. jean-marc.yannou@nxp.com) and the study on an embedded test solution for the RF-MEMS component formed the basis for a new IeMRC project with NXP and others. The work is to our knowledge the first peer reviewed article addressing solder ball reliability and embedded test on this type of SiP platform. RAE_import_type : Journal article RAE_uoa_type : General Engineering

PY - 2007/2/1

Y1 - 2007/2/1

N2 - Purpose – To present key challenges associated with the evolution of system-in-package technologies and present technical work in reliability modeling and embedded test that contributes to these challenges. Design/methodology/approach – Key challenges have been identified from the electronics and integrated MEMS industrial sectors. Solutions to optimising the reliability of a typical assembly process and reducing the cost of production test have been studied through simulation and modelling studies based on technology data released by NXP and in collaboration with EDA tool vendors Coventor and Flomerics. Findings – Characterised models that deliver special and material dependent reliability data that can be used to optimize robustness of SiP assemblies together with results that indicate relative contributions of various structural variables. An initial analytical model for solder ball reliability and a solution for embedding a low cost test for a capacitive RF-MEMS switch identified as an SiP component presenting a key test challenge. Research limitations/implications – Results will contribute to the further development of NXP wafer level system-in-package technology. Limitations are that feedback on the implementation of recommendations and the physical characterisation of the embedded test solution. Originality/value – Both the methodology and associated studies on the structural reliability of an industrial SiP technology are unique. The analytical model for solder ball life is new as is the embedded test solution for the RF-MEMS switch.

AB - Purpose – To present key challenges associated with the evolution of system-in-package technologies and present technical work in reliability modeling and embedded test that contributes to these challenges. Design/methodology/approach – Key challenges have been identified from the electronics and integrated MEMS industrial sectors. Solutions to optimising the reliability of a typical assembly process and reducing the cost of production test have been studied through simulation and modelling studies based on technology data released by NXP and in collaboration with EDA tool vendors Coventor and Flomerics. Findings – Characterised models that deliver special and material dependent reliability data that can be used to optimize robustness of SiP assemblies together with results that indicate relative contributions of various structural variables. An initial analytical model for solder ball reliability and a solution for embedding a low cost test for a capacitive RF-MEMS switch identified as an SiP component presenting a key test challenge. Research limitations/implications – Results will contribute to the further development of NXP wafer level system-in-package technology. Limitations are that feedback on the implementation of recommendations and the physical characterisation of the embedded test solution. Originality/value – Both the methodology and associated studies on the structural reliability of an industrial SiP technology are unique. The analytical model for solder ball life is new as is the embedded test solution for the RF-MEMS switch.

KW - Circuits

KW - Electromechanical devices

KW - Electronics industry

KW - Reliability management

U2 - 10.1108/03056120710723706

DO - 10.1108/03056120710723706

M3 - Journal article

VL - 33

SP - 36

EP - 46

JO - Circuit World

JF - Circuit World

IS - 1

ER -