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Towards a generic programming model for network processors

Research output: Contribution in Book/Report/ProceedingsPaper

Published

Publication date2004
Host publication12th IEEE International Conference on Networks, 2004 (ICON 2004) Vols. 1 & 2 , Proceedings
EditorsL. Wong, Yee-Lee Lau, Hung-Keng Pung, F. Lee, Chen-Khong Tham
Place of publicationNew York
PublisherIEEE
Pages504-510
Number of pages7
Volume2
ISBN (Print)0-7803-8783-X
Original languageEnglish

Conference

Conference12th IEEE International Conference on Networks (ICON 2004)
CitySingapore
Period16/11/0419/11/04

Conference

Conference12th IEEE International Conference on Networks (ICON 2004)
CitySingapore
Period16/11/0419/11/04

Abstract

Network Processors (NPs) are emerging as a cost effective network element technology that can be more readily updated and evolved than custom hardware or ASIC-based designs. Moreover, NPs promise support for run-time reconfiguration of low-level networking software. However, it is notoriously difficult to develop software for NPs because of their complex design, architectural heterogeneity, and demanding performance constraints. In this paper we present a run-time component-based approach to programming NPs. The approach promotes conceptual uniformity and design portability across a wide variety of NP types while simultaneously exploiting hardware assists that are specific to individual NPs. To show how our approach can be applied in a wide range of types of NPs we characterise the design space of NPs and demonstrate the applicability of our concepts to the various classes identified. Then, as a detailed case study, we focus on programming the Intel IXP1200 NP. This demonstrates that our approach can be effectively applied, e.g. in terms of performance, in a demanding real-world NP environment.