Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Conference contribution/Paper › peer-review
Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Conference contribution/Paper › peer-review
}
TY - GEN
T1 - Towards a generic programming model for network processors
AU - Lee, K
AU - Coulson, G
AU - Blair, Gordon
AU - Joolia, A
AU - Ueyama, J
PY - 2004
Y1 - 2004
N2 - Network Processors (NPs) are emerging as a cost effective network element technology that can be more readily updated and evolved than custom hardware or ASIC-based designs. Moreover, NPs promise support for run-time reconfiguration of low-level networking software. However, it is notoriously difficult to develop software for NPs because of their complex design, architectural heterogeneity, and demanding performance constraints. In this paper we present a run-time component-based approach to programming NPs. The approach promotes conceptual uniformity and design portability across a wide variety of NP types while simultaneously exploiting hardware assists that are specific to individual NPs. To show how our approach can be applied in a wide range of types of NPs we characterise the design space of NPs and demonstrate the applicability of our concepts to the various classes identified. Then, as a detailed case study, we focus on programming the Intel IXP1200 NP. This demonstrates that our approach can be effectively applied, e.g. in terms of performance, in a demanding real-world NP environment.
AB - Network Processors (NPs) are emerging as a cost effective network element technology that can be more readily updated and evolved than custom hardware or ASIC-based designs. Moreover, NPs promise support for run-time reconfiguration of low-level networking software. However, it is notoriously difficult to develop software for NPs because of their complex design, architectural heterogeneity, and demanding performance constraints. In this paper we present a run-time component-based approach to programming NPs. The approach promotes conceptual uniformity and design portability across a wide variety of NP types while simultaneously exploiting hardware assists that are specific to individual NPs. To show how our approach can be applied in a wide range of types of NPs we characterise the design space of NPs and demonstrate the applicability of our concepts to the various classes identified. Then, as a detailed case study, we focus on programming the Intel IXP1200 NP. This demonstrates that our approach can be effectively applied, e.g. in terms of performance, in a demanding real-world NP environment.
U2 - 10.1109/ICON.2004.1409218
DO - 10.1109/ICON.2004.1409218
M3 - Conference contribution/Paper
SN - 0-7803-8783-X
VL - 2
SP - 504
EP - 510
BT - 12th IEEE International Conference on Networks, 2004 (ICON 2004) Vols. 1 & 2 , Proceedings
A2 - Wong, L.
A2 - Lau, Yee-Lee
A2 - Pung, Hung-Keng
A2 - Lee, F.
A2 - Tham, Chen-Khong
PB - IEEE
CY - New York
T2 - 12th IEEE International Conference on Networks (ICON 2004)
Y2 - 16 November 2004 through 19 November 2004
ER -