Rights statement: Rights statement: Copyright 2020 American Institute of Physics. This article may be downloaded for personal use only. Any other use requires prior permission of the author and AIP Publishing. This article appeared in Journal of Applied Physics, 128 (3), 2020 and may be found at https://aip.scitation.org/doi/10.1063/5.0011703
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Research output: Contribution to Journal/Magazine › Journal article › peer-review
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TY - JOUR
T1 - Understanding the effect of confinement in scanning spreading resistance microscopy measurements
AU - Pandey, K.
AU - Paredis, K.
AU - Robson, A.J.
AU - Vandervorst, W.
PY - 2020/7/21
Y1 - 2020/7/21
N2 - Scanning spreading resistance microscopy (SSRM) is a powerful technique for quantitative two-and three-dimensional carrier profiling of semiconductor devices with sub-nm spatial resolution. However, considering the sub-10 nm dimensions of advanced devices and the introduction of three-dimensional architectures like fin field effect transistor (FinFET) and nanowires, the measured spreading resistance is easily impacted by parasitic series resistances present in the system. The limited amount of material, the presence of multiple interfaces, and confined current paths may increase the total resistance measured by SSRM beyond the expected spreading resistance, which can ultimately lead to an inaccurate carrier quantification. Here, we report a simulation assisted experimental study to identify the different parameters affecting the SSRM measurements in confined volumes. Experimentally, the two-dimensional current confinement is obtained by progressively thinning down uniformly doped blanket silicon on insulator wafers using scalpel SSRM. The concomitant SSRM provides detailed electrical information as a function of depth up to oxide interface. We show that the resistance is most affected by the interface traps in case of a heterogeneous sample, followed by the intrinsic resistance of the current carrying paths. Furthermore, we show that accurate carrier quantification is ensured for typical back contact distances of 1 μm if the region of interest is at least nine times larger than the probe radius. © 2020 Author(s).
AB - Scanning spreading resistance microscopy (SSRM) is a powerful technique for quantitative two-and three-dimensional carrier profiling of semiconductor devices with sub-nm spatial resolution. However, considering the sub-10 nm dimensions of advanced devices and the introduction of three-dimensional architectures like fin field effect transistor (FinFET) and nanowires, the measured spreading resistance is easily impacted by parasitic series resistances present in the system. The limited amount of material, the presence of multiple interfaces, and confined current paths may increase the total resistance measured by SSRM beyond the expected spreading resistance, which can ultimately lead to an inaccurate carrier quantification. Here, we report a simulation assisted experimental study to identify the different parameters affecting the SSRM measurements in confined volumes. Experimentally, the two-dimensional current confinement is obtained by progressively thinning down uniformly doped blanket silicon on insulator wafers using scalpel SSRM. The concomitant SSRM provides detailed electrical information as a function of depth up to oxide interface. We show that the resistance is most affected by the interface traps in case of a heterogeneous sample, followed by the intrinsic resistance of the current carrying paths. Furthermore, we show that accurate carrier quantification is ensured for typical back contact distances of 1 μm if the region of interest is at least nine times larger than the probe radius. © 2020 Author(s).
KW - Computer architecture
KW - Electric resistance
KW - FinFET
KW - Image segmentation
KW - Silicon on insulator technology
KW - Confined current path
KW - Fin field-effect transistors
KW - Intrinsic resistance
KW - Parasitic series resistance
KW - Scanning spreading resistance microscopy
KW - Silicon on insulator wafers
KW - Spreading resistance
KW - Three-dimensional architecture
KW - Silicon wafers
U2 - 10.1063/5.0011703
DO - 10.1063/5.0011703
M3 - Journal article
VL - 128
JO - Journal of Applied Physics
JF - Journal of Applied Physics
SN - 0021-8979
IS - 3
M1 - 034303
ER -