Results for systolic array processor architecture

Publications & Outputs

1. Low-power systolic array processor architecture for FSBM video motion estimation

   Jiang, M., Crookes, D., Davidson, S. & Turner, R., 28/09/2006, In: Electronics Letters. 42, 20, p. 1146-1148 3 p.

   Research output: Contribution to Journal/Magazine › Journal article › peer-review