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Dr Roshan Weerasekera

Formerly at Lancaster University

  1. 2010
  2. Published

    On signalling over through-silicon via (TSV) interconnects in 3-D integrated circuits.

    Weerasekera, R., Grange, M., Pamunuwa, D. B. & Tenhunen, H., 03/2010, p. 1325-1328. 4 p.

    Research output: Contribution to conference - Without ISBN/ISSN Conference paperpeer-review

  3. 2009
  4. Published

    Compact modelling of through-silicon vias (TSVs) in three-dimensional (3-D) integrated circuits.

    Weerasekera, R., Grange, M., Pamunuwa, D. B., Tenhunen, H. & Zheng, L-R., 10/2009, Proceedings of the IEEE International Conference on 3D System Integration (3D IC), 2009. San Francisco: IEEE

    Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSNChapter

  5. Published

    2-D and 3-D Integration of Heterogeneous Electronic Systems under Cost, Performance and Technological Constraints

    Weerasekera, R., Pamunuwa, D., Zheng, L-R. & Tenhunen, H., 08/2009, In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 28, 8, p. 1237-1250 14 p.

    Research output: Contribution to Journal/MagazineJournal article

  6. Published

    Scalability of Network-on-Chip communication architecture for 3-D meshes.

    Weldezion, A. Y., Grange, M., Pamunuwa, D. B., Lu, Z., Jantsch, A., Weerasekera, R. & Tenhunen, H., 12/06/2009, Proc. ACM/IEEE International Symposium on Networks on Chip (NOCS). San Diego: IEEE, p. 114-123 10 p.

    Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSNChapter

  7. Published

    Bandwidth optimization for through silicon via (TSV) bundles in 3D integrated circuits.

    Weldezion, A., Weerasekera, R., Pamunuwa, D. B., Zheng, L-R. & Tenhunen, H., 2009, Workshop Notes, Design, Automation and Test in Europe (DATE). Nice

    Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSNChapter

  8. Published

    Closed-form equations for through-silicon via (TSV) parasitics in 3-D integrated circuits (ICs).

    Weerasekera, R., Pamunuwa, D. B., Grange, M., Tenhunen, H. & Zheng, L-R., 2009, Workshop Notes, Design, Automation and Test in Europe (DATE). Nice

    Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSNChapter

  9. Published

    Exploration of Through Silicon Via Interconnect Parasitics for 3-Dimensional Integrated Circuits

    Grange, M., Weerasekera, R., Pamunuwa, D. & Tenhunen, H., 2009, Workshop Notes, Design, Automation and Test in Europe (DATE). Nice

    Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSNChapter

  10. Published

    Physical Mapping and Performance Study of a Multi-Clock 3-Dimensional Network-on-Chip Mesh.

    Grange, M., Weldezion, A. Y., Pamunuwa, D. B., Weerasekera, R., Zhonghai, L., Jantsch, A. & Shippen, D., 2009, Proceedings of the IEEE International Conference on 3D System Integration (3D IC), 2009. San Francisco: IEEE

    Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSNChapter

  11. 2008
  12. Published

    Minimal-power, delay-balanced smart repeaters for global interconnects in the nanometer regime.

    Weerasekera, R., Pamunuwa, D. B., Zheng, L-R. & Tenhunen, H., 05/2008, In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 16, 5, p. 589-593 5 p.

    Research output: Contribution to Journal/MagazineJournal articlepeer-review

  13. 2007
  14. Published

    Extending systems-on-chip to the third dimension : performance, cost and technological tradeoffs.

    Weerasekera, R., Zheng, L-R., Pamunuwa, D. B. & Tenhunen, H., 11/2007, Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD). San Jose, California: IEEE, p. 212-219 8 p.

    Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSNChapter

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