Home > Research > Publications & Outputs

Research

Publications and Research Outputs

« Simple search

Reset

to
84101 - 84110 out of 98,571Page size: 10
  1. Published

    Simple frequency counting techniques for analysis of VCO/CP-PLL coupled noise sensitivity in fully embedded CP-PLLs.

    Burbidge, M. J., 2004, Proceedings of the 2nd IEE integrated circuit test conference.

    Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

  2. Published

    Motivations and techniques of built in self-test for embedded frequency synthesis systems incorporating charge pump phase-locked loops.

    Burbidge, M., Lechner, A., Bell, G. & Richardson, A. M. D., 2004, IEE proceedings - circuits, devices and systems. 4 ed. Vol. 151. p. 337-348 12 p.

    Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

  3. Published

    Evaluation and detection of deterministic jitter causes in CP-PLLs due to macro level faults and pre-detection using simple methods.

    Burbidge, M. J., Lechner, A. & Richardson, A. M. D., 2003, In: Proceedings of the 9th IEEE international mixed signal test workshop (IMSTW03). p. 157-164 8 p.

    Research output: Contribution to Journal/Magazine › Journal article

  4. Published

    Investigations for minimum invasion digital only built in ‘ramp’ based test techniques for charge pump PLLs.

    Burbidge, M. J., Poullet, F., Tijou, J. & Richardson, A. M. D., 08/2003, In: Journal of Electronic Testing. 19, 4, p. 481-490 10 p.

    Research output: Contribution to Journal/Magazine › Journal article

  5. Published

    Investigations of automatic built in transient step response monitoring for embedded second order charge pump phase locked loop frequency synthesizers.

    Burbidge, M. J., Tijou, J. & Richardson, A. M. D., 2003, In: Journal of Electronic Testing.

    Research output: Contribution to Journal/Magazine › Journal article

  6. Published

    Techniques for automatic on chip closed loop transfer function monitoring for embedded charge pump phase locked loops.

    Burbidge, M. J., Tijou, J. & Richardson, A. M. D., 19/12/2003, Design, Automation and Test in Europe Conference and Exhibition, 2003. p. 496-501 6 p.

    Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

  7. Published

    Investigations for minimum invasion digital only built in ‘ramp’ based test techniques for charge pump PLLs.

    Burbidge, M. J., Tijou, J., Poullet, F. & Richardson, A. M. D., 2002, Proceedings of the Seventh IEEE European Test Workshop, 2002.. IEEE, p. 95-102 8 p.

    Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

  8. Published

    Investigations of automatic built in transient step response monitoring for embedded second order charge pump phase locked loop frequency synthesisers.

    Burbidge, M. J. & Tijou, J. R., 2002, Proceedings of the 8th IEEE mixed signal test workshop.

    Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

  9. Published

    Simple digital only test approach for embedded charge-pump phase-locked loops.

    Burbidge, M. & Richardson, A. M. D., 2001, In: Electronics Letters. 37, 22, p. 1318-1319 2 p.

    Research output: Contribution to Journal/Magazine › Journal article

  10. Published

    Test techniques for embedded charge pump phase-locked loops: problems, current BIST techniques and alternative suggestions.

    Burbidge, M., Richardson, A. M. D. & Lechner, A., 2001, Proceedings of the 7th IEEE international test workshop. p. 97-102 6 p.

    Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

Previous 1...8407 8408 8409 8410 8411 8412 8413 8414 ...9858 Next

Back to top