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  • ULTRARAM-TED v4.2

    Accepted author manuscript, 817 KB, PDF document

    Available under license: CC BY: Creative Commons Attribution 4.0 International License

  • Lane Trans Electron Devices 68 2271 (2021)

    Final published version, 1.16 MB, PDF document

    Available under license: CC BY: Creative Commons Attribution 4.0 International License

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ULTRARAM: toward the development of a III-V semiconductor, non-volatile, random-access memory

Research output: Contribution to Journal/Magazine › Journal article › peer-review

Published

Standard

ULTRARAM: toward the development of a III-V semiconductor, non-volatile, random-access memory. / Lane, Dominic; Hodgson, Peter; Potter, Richard et al.
In: IEEE Transactions on Electron Devices, Vol. 68, No. 5, 31.05.2021, p. 2271-2274.

Research output: Contribution to Journal/Magazine › Journal article › peer-review

Harvard

Lane, D, Hodgson, P, Potter, R, Beanland, R & Hayne, M 2021, 'ULTRARAM: toward the development of a III-V semiconductor, non-volatile, random-access memory', IEEE Transactions on Electron Devices, vol. 68, no. 5, pp. 2271-2274. https://doi.org/10.1109/TED.2021.3064788

APA

Lane, D., Hodgson, P., Potter, R., Beanland, R., & Hayne, M. (2021). ULTRARAM: toward the development of a III-V semiconductor, non-volatile, random-access memory. IEEE Transactions on Electron Devices, 68(5), 2271-2274. https://doi.org/10.1109/TED.2021.3064788

Vancouver

Lane D, Hodgson P, Potter R, Beanland R, Hayne M. ULTRARAM: toward the development of a III-V semiconductor, non-volatile, random-access memory. IEEE Transactions on Electron Devices. 2021 May 31;68(5):2271-2274. Epub 2021 Mar 25. doi: 10.1109/TED.2021.3064788

Author

Lane, Dominic ; Hodgson, Peter ; Potter, Richard et al. / ULTRARAM : toward the development of a III-V semiconductor, non-volatile, random-access memory. In: IEEE Transactions on Electron Devices. 2021 ; Vol. 68, No. 5. pp. 2271-2274.

Bibtex

@article{708638a62c4848a58c577809629c106c,
title = "ULTRARAM: toward the development of a III-V semiconductor, non-volatile, random-access memory",
abstract = "ULTRARAM{\texttrademark} is a III-V compound semiconductor memory concept which exploits quantum resonant tunneling to achieve non-volatility at extremely low switching energy per unit area. Prototype devices are fabricated in a 2x2 memory array formation on GaAs substrates. The devices show 0/1 state contrast from program/erase (P/E) cycles with 2.5 V pulses of 500-µs duration, a remarkable switching speed for a 20 µm gate length. Memory retention is tested for 8x104 s, whereby the 0/1 states show adequate contrast throughout, whilst performing 8x104 readout operations. Further reliability is demonstrated via program-read-erase-read endurance cycling for 106 cycles with 0/1 contrast. A half-voltage array architecture proposed in our previous work is experimentally realized, with an outstandingly small disturb rate over 105 half-voltage cycles.",
author = "Dominic Lane and Peter Hodgson and Richard Potter and Richard Beanland and Manus Hayne",
year = "2021",
month = may,
day = "31",
doi = "10.1109/TED.2021.3064788",
language = "English",
volume = "68",
pages = "2271--2274",
journal = "IEEE Transactions on Electron Devices",
issn = "0018-9383",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "5",

}

RIS

TY - JOUR

T1 - ULTRARAM

T2 - toward the development of a III-V semiconductor, non-volatile, random-access memory

AU - Lane, Dominic

AU - Hodgson, Peter

AU - Potter, Richard

AU - Beanland, Richard

AU - Hayne, Manus

PY - 2021/5/31

Y1 - 2021/5/31

N2 - ULTRARAM™ is a III-V compound semiconductor memory concept which exploits quantum resonant tunneling to achieve non-volatility at extremely low switching energy per unit area. Prototype devices are fabricated in a 2x2 memory array formation on GaAs substrates. The devices show 0/1 state contrast from program/erase (P/E) cycles with 2.5 V pulses of 500-µs duration, a remarkable switching speed for a 20 µm gate length. Memory retention is tested for 8x104 s, whereby the 0/1 states show adequate contrast throughout, whilst performing 8x104 readout operations. Further reliability is demonstrated via program-read-erase-read endurance cycling for 106 cycles with 0/1 contrast. A half-voltage array architecture proposed in our previous work is experimentally realized, with an outstandingly small disturb rate over 105 half-voltage cycles.

AB - ULTRARAM™ is a III-V compound semiconductor memory concept which exploits quantum resonant tunneling to achieve non-volatility at extremely low switching energy per unit area. Prototype devices are fabricated in a 2x2 memory array formation on GaAs substrates. The devices show 0/1 state contrast from program/erase (P/E) cycles with 2.5 V pulses of 500-µs duration, a remarkable switching speed for a 20 µm gate length. Memory retention is tested for 8x104 s, whereby the 0/1 states show adequate contrast throughout, whilst performing 8x104 readout operations. Further reliability is demonstrated via program-read-erase-read endurance cycling for 106 cycles with 0/1 contrast. A half-voltage array architecture proposed in our previous work is experimentally realized, with an outstandingly small disturb rate over 105 half-voltage cycles.

U2 - 10.1109/TED.2021.3064788

DO - 10.1109/TED.2021.3064788

M3 - Journal article

VL - 68

SP - 2271

EP - 2274

JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

SN - 0018-9383

IS - 5

ER -