Research output: Contribution to journal › Journal article
|<mark>Journal publication date</mark>||12/1996|
|<mark>Journal</mark>||IEE Proceedings - Circuits, Devices and Systems|
|Number of pages||6|
The integration of design-for-test (Dft) features into complex integrated circuits (ICs) to support exhaustive, fast, and therefore economic testing is becoming crucial to the manufacturing process. The authors investigate the effectiveness of two different test strategies for a current-mode digital-to-analogue converter (DAC) and DfT methods for optimising the design at the transistor level. The first approach is a standard functional test; the second, a novel parametric test strategy with on-chip support. Both strategies are supplemented by an I-ssq screen for the digital components. The evaluation process used to compare the effectiveness of these two test strategies shows that both approaches result in similar fault coverage figures and a number of simple circuit level design changes can enhance the fault coverage and reduce the size of the test set.