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Design-for-test (DfT) study on a current mode DAC

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Design-for-test (DfT) study on a current mode DAC. / Olbrich, T ; Mozuelos, R ; Richardson, A et al.
In: IEE Proceedings - Circuits, Devices and Systems, Vol. 143, No. 6, 12.1996, p. 374-379.

Research output: Contribution to Journal/Magazine › Journal article › peer-review

Harvard

Olbrich, T, Mozuelos, R, Richardson, A & Bracho, S 1996, 'Design-for-test (DfT) study on a current mode DAC', IEE Proceedings - Circuits, Devices and Systems, vol. 143, no. 6, pp. 374-379. https://doi.org/10.1049/ip-cds:19960956

APA

Olbrich, T., Mozuelos, R., Richardson, A., & Bracho, S. (1996). Design-for-test (DfT) study on a current mode DAC. IEE Proceedings - Circuits, Devices and Systems, 143(6), 374-379. https://doi.org/10.1049/ip-cds:19960956

Vancouver

Olbrich T, Mozuelos R, Richardson A, Bracho S. Design-for-test (DfT) study on a current mode DAC. IEE Proceedings - Circuits, Devices and Systems. 1996 Dec;143(6):374-379. doi: 10.1049/ip-cds:19960956

Author

Olbrich, T ; Mozuelos, R ; Richardson, A et al. / Design-for-test (DfT) study on a current mode DAC. In: IEE Proceedings - Circuits, Devices and Systems. 1996 ; Vol. 143, No. 6. pp. 374-379.

Bibtex

@article{56554669e3294daa9d58a99cc60a8372,
title = "Design-for-test (DfT) study on a current mode DAC",
abstract = "The integration of design-for-test (Dft) features into complex integrated circuits (ICs) to support exhaustive, fast, and therefore economic testing is becoming crucial to the manufacturing process. The authors investigate the effectiveness of two different test strategies for a current-mode digital-to-analogue converter (DAC) and DfT methods for optimising the design at the transistor level. The first approach is a standard functional test; the second, a novel parametric test strategy with on-chip support. Both strategies are supplemented by an I-ssq screen for the digital components. The evaluation process used to compare the effectiveness of these two test strategies shows that both approaches result in similar fault coverage figures and a number of simple circuit level design changes can enhance the fault coverage and reduce the size of the test set.",
keywords = "design-for-test, DAC, mixed signal test, analogue test",
author = "T Olbrich and R Mozuelos and A Richardson and S Bracho",
year = "1996",
month = dec,
doi = "10.1049/ip-cds:19960956",
language = "English",
volume = "143",
pages = "374--379",
journal = "IEE Proceedings - Circuits, Devices and Systems",
issn = "1350-2409",
publisher = "Institute of Electrical Engineers",
number = "6",

}

RIS

TY - JOUR

T1 - Design-for-test (DfT) study on a current mode DAC

AU - Olbrich, T

AU - Mozuelos, R

AU - Richardson, A

AU - Bracho, S

PY - 1996/12

Y1 - 1996/12

N2 - The integration of design-for-test (Dft) features into complex integrated circuits (ICs) to support exhaustive, fast, and therefore economic testing is becoming crucial to the manufacturing process. The authors investigate the effectiveness of two different test strategies for a current-mode digital-to-analogue converter (DAC) and DfT methods for optimising the design at the transistor level. The first approach is a standard functional test; the second, a novel parametric test strategy with on-chip support. Both strategies are supplemented by an I-ssq screen for the digital components. The evaluation process used to compare the effectiveness of these two test strategies shows that both approaches result in similar fault coverage figures and a number of simple circuit level design changes can enhance the fault coverage and reduce the size of the test set.

AB - The integration of design-for-test (Dft) features into complex integrated circuits (ICs) to support exhaustive, fast, and therefore economic testing is becoming crucial to the manufacturing process. The authors investigate the effectiveness of two different test strategies for a current-mode digital-to-analogue converter (DAC) and DfT methods for optimising the design at the transistor level. The first approach is a standard functional test; the second, a novel parametric test strategy with on-chip support. Both strategies are supplemented by an I-ssq screen for the digital components. The evaluation process used to compare the effectiveness of these two test strategies shows that both approaches result in similar fault coverage figures and a number of simple circuit level design changes can enhance the fault coverage and reduce the size of the test set.

KW - design-for-test

KW - DAC

KW - mixed signal test

KW - analogue test

U2 - 10.1049/ip-cds:19960956

DO - 10.1049/ip-cds:19960956

M3 - Journal article

VL - 143

SP - 374

EP - 379

JO - IEE Proceedings - Circuits, Devices and Systems

JF - IEE Proceedings - Circuits, Devices and Systems

SN - 1350-2409

IS - 6

ER -