A global wire planning scheme for Network-on-Chip.

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A global wire planning scheme for Network-on-Chip. / Liu, J.; Zheng, Li-Rong; Pamunuwa, Dinesh B. et al.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.. Vol. 4 2003. p. IV-892-IV-895.

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

Harvard

Liu, J, Zheng, L-R, Pamunuwa, DB & Tenhunen, H 2003, A global wire planning scheme for Network-on-Chip. in Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.. vol. 4, pp. IV-892-IV-895. <http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1206364>

APA

Liu, J., Zheng, L.-R., Pamunuwa, D. B., & Tenhunen, H. (2003). A global wire planning scheme for Network-on-Chip. In Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03. (Vol. 4, pp. IV-892-IV-895) http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1206364

Vancouver

Liu J, Zheng LR, Pamunuwa DB, Tenhunen H. A global wire planning scheme for Network-on-Chip. In Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.. Vol. 4. 2003. p. IV-892-IV-895

Author

Liu, J. ; Zheng, Li-Rong ; Pamunuwa, Dinesh B. et al. / A global wire planning scheme for Network-on-Chip. Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.. Vol. 4 2003. pp. IV-892-IV-895

Bibtex

@inbook{3265b3936d47433e94177a8975f69f63,

title = "A global wire planning scheme for Network-on-Chip.",

abstract = "As technology scales down, the interconnect for on-chip global communication becomes the delay bottleneck. In order to provide well-controlled global wire delay and efficient global communication, a packet switched Network-on-Chip (NoC) architecture was proposed by different authors. In this paper, the NoC system parameters constrained by the interconnections are studied. Predictions on scaled system parameters such as clock frequency, resource size, global communication bandwidth and inter-resource delay are made for future technologies. Based on these parameters, a global wire planning scheme is proposed.",

author = "J. Liu and Li-Rong Zheng and Pamunuwa, {Dinesh B.} and Hannu Tenhunen",

note = "{"}{\textcopyright}2003 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.{"} {"}This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.{"}",

year = "2003",

language = "English",

isbn = "0-7803-7761-3",

volume = "4",

pages = "IV--892--IV--895",

booktitle = "Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.",

}

RIS

TY - CHAP

T1 - A global wire planning scheme for Network-on-Chip.

AU - Liu, J.

AU - Zheng, Li-Rong

AU - Pamunuwa, Dinesh B.

AU - Tenhunen, Hannu

N1 - "©2003 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE." "This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder."

PY - 2003

Y1 - 2003

N2 - As technology scales down, the interconnect for on-chip global communication becomes the delay bottleneck. In order to provide well-controlled global wire delay and efficient global communication, a packet switched Network-on-Chip (NoC) architecture was proposed by different authors. In this paper, the NoC system parameters constrained by the interconnections are studied. Predictions on scaled system parameters such as clock frequency, resource size, global communication bandwidth and inter-resource delay are made for future technologies. Based on these parameters, a global wire planning scheme is proposed.

AB - As technology scales down, the interconnect for on-chip global communication becomes the delay bottleneck. In order to provide well-controlled global wire delay and efficient global communication, a packet switched Network-on-Chip (NoC) architecture was proposed by different authors. In this paper, the NoC system parameters constrained by the interconnections are studied. Predictions on scaled system parameters such as clock frequency, resource size, global communication bandwidth and inter-resource delay are made for future technologies. Based on these parameters, a global wire planning scheme is proposed.

M3 - Chapter

SN - 0-7803-7761-3

VL - 4

SP - IV-892-IV-895

BT - Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.

ER -

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