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Accurate a priori signal integrity estimation using a multilevel dynamic interconnect model for deep submicron VLSI design.

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Accurate a priori signal integrity estimation using a multilevel dynamic interconnect model for deep submicron VLSI design. / Zheng, Li-Rong; Pamunuwa, Dinesh B.; Tenhunen, Hannu.
Proceedings of the 26th European Solid-State Circuits Conference, 2000. ESSCIRC '00.. IEEE, 2000. p. 352-355.

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

Harvard

Zheng, L-R, Pamunuwa, DB & Tenhunen, H 2000, Accurate a priori signal integrity estimation using a multilevel dynamic interconnect model for deep submicron VLSI design. in Proceedings of the 26th European Solid-State Circuits Conference, 2000. ESSCIRC '00.. IEEE, pp. 352-355. <http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1471284>

APA

Zheng, L.-R., Pamunuwa, D. B., & Tenhunen, H. (2000). Accurate a priori signal integrity estimation using a multilevel dynamic interconnect model for deep submicron VLSI design. In Proceedings of the 26th European Solid-State Circuits Conference, 2000. ESSCIRC '00. (pp. 352-355). IEEE. http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1471284

Vancouver

Zheng LR, Pamunuwa DB, Tenhunen H. Accurate a priori signal integrity estimation using a multilevel dynamic interconnect model for deep submicron VLSI design. In Proceedings of the 26th European Solid-State Circuits Conference, 2000. ESSCIRC '00.. IEEE. 2000. p. 352-355

Author

Zheng, Li-Rong ; Pamunuwa, Dinesh B. ; Tenhunen, Hannu. / Accurate a priori signal integrity estimation using a multilevel dynamic interconnect model for deep submicron VLSI design. Proceedings of the 26th European Solid-State Circuits Conference, 2000. ESSCIRC '00.. IEEE, 2000. pp. 352-355

Bibtex

@inbook{a4f307daddce4618a9132885171be4f9,
title = "Accurate a priori signal integrity estimation using a multilevel dynamic interconnect model for deep submicron VLSI design.",
abstract = "A multilevel dynamic interconnect model was derived for accurate a priori signal integrity estimates. Cross-talk and delay estimations over interconnects in deep submicron technology were analyzed systematically using this model. Good accuracy and excellent time-efficiency were found compared with electromagnetic simulations. We aim to build a dynamic interconnect library with this model to facilitate the interconnect issues for future VLSI design.",
author = "Li-Rong Zheng and Pamunuwa, {Dinesh B.} and Hannu Tenhunen",
note = "{"}{\textcopyright}2000 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.{"} {"}This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.{"}",
year = "2000",
language = "English",
pages = "352--355",
booktitle = "Proceedings of the 26th European Solid-State Circuits Conference, 2000. ESSCIRC '00.",
publisher = "IEEE",

}

RIS

TY - CHAP

T1 - Accurate a priori signal integrity estimation using a multilevel dynamic interconnect model for deep submicron VLSI design.

AU - Zheng, Li-Rong

AU - Pamunuwa, Dinesh B.

AU - Tenhunen, Hannu

N1 - "©2000 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE." "This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder."

PY - 2000

Y1 - 2000

N2 - A multilevel dynamic interconnect model was derived for accurate a priori signal integrity estimates. Cross-talk and delay estimations over interconnects in deep submicron technology were analyzed systematically using this model. Good accuracy and excellent time-efficiency were found compared with electromagnetic simulations. We aim to build a dynamic interconnect library with this model to facilitate the interconnect issues for future VLSI design.

AB - A multilevel dynamic interconnect model was derived for accurate a priori signal integrity estimates. Cross-talk and delay estimations over interconnects in deep submicron technology were analyzed systematically using this model. Good accuracy and excellent time-efficiency were found compared with electromagnetic simulations. We aim to build a dynamic interconnect library with this model to facilitate the interconnect issues for future VLSI design.

M3 - Chapter

SP - 352

EP - 355

BT - Proceedings of the 26th European Solid-State Circuits Conference, 2000. ESSCIRC '00.

PB - IEEE

ER -