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Class AB cascode current memory cell.

Research output: Contribution to Journal/Magazine › Journal article

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Class AB cascode current memory cell. / Bratt, Adrian; Olbrich, T.; Dorey, A. P.
In: Electronics Letters, Vol. 30, No. 22, 10.1994, p. 1821-1823.

Research output: Contribution to Journal/Magazine › Journal article

Harvard

Bratt, A, Olbrich, T & Dorey, AP 1994, 'Class AB cascode current memory cell.', Electronics Letters, vol. 30, no. 22, pp. 1821-1823. <http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=7813&arnumber=329961&count=60&index=7>

APA

Bratt, A., Olbrich, T., & Dorey, A. P. (1994). Class AB cascode current memory cell. Electronics Letters, 30(22), 1821-1823. http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=7813&arnumber=329961&count=60&index=7

Vancouver

Bratt A, Olbrich T, Dorey AP. Class AB cascode current memory cell. Electronics Letters. 1994 Oct;30(22):1821-1823.

Author

Bratt, Adrian ; Olbrich, T. ; Dorey, A. P. / Class AB cascode current memory cell. In: Electronics Letters. 1994 ; Vol. 30, No. 22. pp. 1821-1823.

Bibtex

@article{a9b1d3baa59d4998a454df199ad9496f,
title = "Class AB cascode current memory cell.",
abstract = "The presented sampled-current memory cell demonstrates class AB operation where the bipolar input current magnitude may exceed twice the quiescent bias current even though full cascode regulation is maintained. Calculation of the necessary safety margin to accommodate process tolerances is shown to be simplified compared with the standard regulated cascode cell.",
keywords = "bipolar integrated circuits, cascade networks, integrated memory circuits, switched networks",
author = "Adrian Bratt and T. Olbrich and Dorey, {A. P.}",
note = "{"}{\textcopyright}1994 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.{"} {"}This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.{"}",
year = "1994",
month = oct,
language = "English",
volume = "30",
pages = "1821--1823",
journal = "Electronics Letters",
issn = "1350-911X",
publisher = "Institution of Engineering and Technology",
number = "22",

}

RIS

TY - JOUR

T1 - Class AB cascode current memory cell.

AU - Bratt, Adrian

AU - Olbrich, T.

AU - Dorey, A. P.

N1 - "©1994 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE." "This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder."

PY - 1994/10

Y1 - 1994/10

N2 - The presented sampled-current memory cell demonstrates class AB operation where the bipolar input current magnitude may exceed twice the quiescent bias current even though full cascode regulation is maintained. Calculation of the necessary safety margin to accommodate process tolerances is shown to be simplified compared with the standard regulated cascode cell.

AB - The presented sampled-current memory cell demonstrates class AB operation where the bipolar input current magnitude may exceed twice the quiescent bias current even though full cascode regulation is maintained. Calculation of the necessary safety margin to accommodate process tolerances is shown to be simplified compared with the standard regulated cascode cell.

KW - bipolar integrated circuits

KW - cascade networks

KW - integrated memory circuits

KW - switched networks

M3 - Journal article

VL - 30

SP - 1821

EP - 1823

JO - Electronics Letters

JF - Electronics Letters

SN - 1350-911X

IS - 22

ER -