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Enhanced trellis extracted synchronisation technique for practical implementation

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSNConference contribution/Paperpeer-review

Published

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Enhanced trellis extracted synchronisation technique for practical implementation. / Lund, David ; Honary, Bahram.
Novel DSP Algorithms and Architectures for Radio Systems IEE Colloquium on. London: IEEE, 1999. p. 5/1-5/5.

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSNConference contribution/Paperpeer-review

Harvard

Lund, D & Honary, B 1999, Enhanced trellis extracted synchronisation technique for practical implementation. in Novel DSP Algorithms and Architectures for Radio Systems IEE Colloquium on. IEEE, London, pp. 5/1-5/5. https://doi.org/10.1049/ic:19990847

APA

Lund, D., & Honary, B. (1999). Enhanced trellis extracted synchronisation technique for practical implementation. In Novel DSP Algorithms and Architectures for Radio Systems IEE Colloquium on (pp. 5/1-5/5). IEEE. https://doi.org/10.1049/ic:19990847

Vancouver

Lund D, Honary B. Enhanced trellis extracted synchronisation technique for practical implementation. In Novel DSP Algorithms and Architectures for Radio Systems IEE Colloquium on. London: IEEE. 1999. p. 5/1-5/5 doi: 10.1049/ic:19990847

Author

Lund, David ; Honary, Bahram. / Enhanced trellis extracted synchronisation technique for practical implementation. Novel DSP Algorithms and Architectures for Radio Systems IEE Colloquium on. London : IEEE, 1999. pp. 5/1-5/5

Bibtex

@inproceedings{d2acf5daa3a146c8bef63f6d16983c27,
title = "Enhanced trellis extracted synchronisation technique for practical implementation",
abstract = "Intrinsic synchronisation algorithms increase the data throughput of a system at the expense of processing. The trellis extracted synchronisation technique (TEST) is an intrinsic synchronisation algorithm for the combined decoding and synchronisation of error control block codes. This paper illustrates two enhancements to the TEST algorithm which improves synchronisation performance and reduces processing. Inherent errors due to the linearity and cyclic properties of block codes are corrected. A simple estimate of future synchronisation points in a data stream can be efficiently used to decrease the processing with no expense of coding performance",
author = "David Lund and Bahram Honary",
year = "1999",
month = sep,
doi = "10.1049/ic:19990847",
language = "English",
pages = "5/1--5/5",
booktitle = "Novel DSP Algorithms and Architectures for Radio Systems IEE Colloquium on",
publisher = "IEEE",

}

RIS

TY - GEN

T1 - Enhanced trellis extracted synchronisation technique for practical implementation

AU - Lund, David

AU - Honary, Bahram

PY - 1999/9

Y1 - 1999/9

N2 - Intrinsic synchronisation algorithms increase the data throughput of a system at the expense of processing. The trellis extracted synchronisation technique (TEST) is an intrinsic synchronisation algorithm for the combined decoding and synchronisation of error control block codes. This paper illustrates two enhancements to the TEST algorithm which improves synchronisation performance and reduces processing. Inherent errors due to the linearity and cyclic properties of block codes are corrected. A simple estimate of future synchronisation points in a data stream can be efficiently used to decrease the processing with no expense of coding performance

AB - Intrinsic synchronisation algorithms increase the data throughput of a system at the expense of processing. The trellis extracted synchronisation technique (TEST) is an intrinsic synchronisation algorithm for the combined decoding and synchronisation of error control block codes. This paper illustrates two enhancements to the TEST algorithm which improves synchronisation performance and reduces processing. Inherent errors due to the linearity and cyclic properties of block codes are corrected. A simple estimate of future synchronisation points in a data stream can be efficiently used to decrease the processing with no expense of coding performance

U2 - 10.1049/ic:19990847

DO - 10.1049/ic:19990847

M3 - Conference contribution/Paper

SP - 5/1-5/5

BT - Novel DSP Algorithms and Architectures for Radio Systems IEE Colloquium on

PB - IEEE

CY - London

ER -