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Forwarding path architectures for multicore software routers

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Conference contribution/Paper › peer-review

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Forwarding path architectures for multicore software routers. / Egi, Norbert; Greenhalgh, Adam; Handley, Mark et al.
PRESTO '10: Proceedings of the Workshop on Programmable Routers for Extensible Services of Tomorrow. New York, NY, USA: ACM, 2010. p. 1-6.

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Conference contribution/Paper › peer-review

Harvard

Egi, N, Greenhalgh, A, Handley, M, Hoerdt, M, Huici, F, Mathy, L & Papadimitriou, P 2010, Forwarding path architectures for multicore software routers. in PRESTO '10: Proceedings of the Workshop on Programmable Routers for Extensible Services of Tomorrow. ACM, New York, NY, USA, pp. 1-6. https://doi.org/10.1145/1921151.1921155

APA

Egi, N., Greenhalgh, A., Handley, M., Hoerdt, M., Huici, F., Mathy, L., & Papadimitriou, P. (2010). Forwarding path architectures for multicore software routers. In PRESTO '10: Proceedings of the Workshop on Programmable Routers for Extensible Services of Tomorrow (pp. 1-6). ACM. https://doi.org/10.1145/1921151.1921155

Vancouver

Egi N, Greenhalgh A, Handley M, Hoerdt M, Huici F, Mathy L et al. Forwarding path architectures for multicore software routers. In PRESTO '10: Proceedings of the Workshop on Programmable Routers for Extensible Services of Tomorrow. New York, NY, USA: ACM. 2010. p. 1-6 doi: 10.1145/1921151.1921155

Author

Egi, Norbert ; Greenhalgh, Adam ; Handley, Mark et al. / Forwarding path architectures for multicore software routers. PRESTO '10: Proceedings of the Workshop on Programmable Routers for Extensible Services of Tomorrow. New York, NY, USA : ACM, 2010. pp. 1-6

Bibtex

@inproceedings{5b090ba8459d406eb44f6d5f8de2ec35,
title = "Forwarding path architectures for multicore software routers",
abstract = "Multi-core CPUs, along with recent advances in memory and buses, render commodity hardware a strong candidate for building fexible and high-performance software routers. With a forwarding plane physically composed of many packet processing components and operations, resource allocation in multi-core systems is not trivial. Indeed, packets crossing cache hierarchies degrade forwarding performance, since the bottleneck is main memory access. Therefore, forwarding path allocation and input/output processing become challenging, especially when states and data structures have to be shared among multiple cores. In this context, we investigate a set of input/output processing architectures, as well as resource allocation strategies for forwarding paths. For each packet processing operation, we uncover the gains and possible implications by either running different components concurrently or replicating the same components across different cores.",
author = "Norbert Egi and Adam Greenhalgh and Mark Handley and Mickael Hoerdt and Felipe Huici and Laurent Mathy and Panagiotis Papadimitriou",
year = "2010",
doi = "10.1145/1921151.1921155",
language = "English",
isbn = "978-1-4503-0467-2",
pages = "1--6",
booktitle = "PRESTO '10: Proceedings of the Workshop on Programmable Routers for Extensible Services of Tomorrow",
publisher = "ACM",

}

RIS

TY - GEN

T1 - Forwarding path architectures for multicore software routers

AU - Egi, Norbert

AU - Greenhalgh, Adam

AU - Handley, Mark

AU - Hoerdt, Mickael

AU - Huici, Felipe

AU - Mathy, Laurent

AU - Papadimitriou, Panagiotis

PY - 2010

Y1 - 2010

N2 - Multi-core CPUs, along with recent advances in memory and buses, render commodity hardware a strong candidate for building fexible and high-performance software routers. With a forwarding plane physically composed of many packet processing components and operations, resource allocation in multi-core systems is not trivial. Indeed, packets crossing cache hierarchies degrade forwarding performance, since the bottleneck is main memory access. Therefore, forwarding path allocation and input/output processing become challenging, especially when states and data structures have to be shared among multiple cores. In this context, we investigate a set of input/output processing architectures, as well as resource allocation strategies for forwarding paths. For each packet processing operation, we uncover the gains and possible implications by either running different components concurrently or replicating the same components across different cores.

AB - Multi-core CPUs, along with recent advances in memory and buses, render commodity hardware a strong candidate for building fexible and high-performance software routers. With a forwarding plane physically composed of many packet processing components and operations, resource allocation in multi-core systems is not trivial. Indeed, packets crossing cache hierarchies degrade forwarding performance, since the bottleneck is main memory access. Therefore, forwarding path allocation and input/output processing become challenging, especially when states and data structures have to be shared among multiple cores. In this context, we investigate a set of input/output processing architectures, as well as resource allocation strategies for forwarding paths. For each packet processing operation, we uncover the gains and possible implications by either running different components concurrently or replicating the same components across different cores.

U2 - 10.1145/1921151.1921155

DO - 10.1145/1921151.1921155

M3 - Conference contribution/Paper

SN - 978-1-4503-0467-2

SP - 1

EP - 6

BT - PRESTO '10: Proceedings of the Workshop on Programmable Routers for Extensible Services of Tomorrow

PB - ACM

CY - New York, NY, USA

ER -