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High-performance 3D median filter architecture for medical image despeckling

Research output: Contribution to Journal/Magazine › Journal article › peer-review

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High-performance 3D median filter architecture for medical image despeckling. / Jiang, M.; Crookes, D.
In: Electronics Letters, Vol. 42, No. 24, 23.11.2006, p. 1379-1381.

Research output: Contribution to Journal/Magazine › Journal article › peer-review

Harvard

Jiang, M & Crookes, D 2006, 'High-performance 3D median filter architecture for medical image despeckling', Electronics Letters, vol. 42, no. 24, pp. 1379-1381. https://doi.org/10.1049/el:20062357

APA

Jiang, M., & Crookes, D. (2006). High-performance 3D median filter architecture for medical image despeckling. Electronics Letters, 42(24), 1379-1381. https://doi.org/10.1049/el:20062357

Vancouver

Jiang M, Crookes D. High-performance 3D median filter architecture for medical image despeckling. Electronics Letters. 2006 Nov 23;42(24):1379-1381. doi: 10.1049/el:20062357

Author

Jiang, M. ; Crookes, D. / High-performance 3D median filter architecture for medical image despeckling. In: Electronics Letters. 2006 ; Vol. 42, No. 24. pp. 1379-1381.

Bibtex

@article{c73e94b757534549a28f7d46c5cf61f9,
title = "High-performance 3D median filter architecture for medical image despeckling",
abstract = "A high-sample rate 3D median filtering processor architecture is proposed, based on a novel 3D median filtering algorithm, that can reduce the computing complexity in comparison with the traditional bubble sorting algorithm. A 3times3times3 filter processor is implemented in VHDL, and the simulation verifies that the processor can process a 128times128times96 MRI image in 0.03 seconds while running at 50 MHz",
keywords = "3D median filter, medical image despeckling, computing complexity, filter processor, VHDL, 50 MHz, 0.03 s",
author = "M. Jiang and D. Crookes",
year = "2006",
month = nov,
day = "23",
doi = "10.1049/el:20062357",
language = "English",
volume = "42",
pages = "1379--1381",
journal = "Electronics Letters",
issn = "0013-5194",
publisher = "Institution of Engineering and Technology",
number = "24",

}

RIS

TY - JOUR

T1 - High-performance 3D median filter architecture for medical image despeckling

AU - Jiang, M.

AU - Crookes, D.

PY - 2006/11/23

Y1 - 2006/11/23

N2 - A high-sample rate 3D median filtering processor architecture is proposed, based on a novel 3D median filtering algorithm, that can reduce the computing complexity in comparison with the traditional bubble sorting algorithm. A 3times3times3 filter processor is implemented in VHDL, and the simulation verifies that the processor can process a 128times128times96 MRI image in 0.03 seconds while running at 50 MHz

AB - A high-sample rate 3D median filtering processor architecture is proposed, based on a novel 3D median filtering algorithm, that can reduce the computing complexity in comparison with the traditional bubble sorting algorithm. A 3times3times3 filter processor is implemented in VHDL, and the simulation verifies that the processor can process a 128times128times96 MRI image in 0.03 seconds while running at 50 MHz

KW - 3D median filter

KW - medical image despeckling

KW - computing complexity

KW - filter processor

KW - VHDL

KW - 50 MHz

KW - 0.03 s

U2 - 10.1049/el:20062357

DO - 10.1049/el:20062357

M3 - Journal article

VL - 42

SP - 1379

EP - 1381

JO - Electronics Letters

JF - Electronics Letters

SN - 0013-5194

IS - 24

ER -