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Low-power systolic array processor architecture for FSBM video motion estimation

Research output: Contribution to Journal/Magazine › Journal article › peer-review

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Low-power systolic array processor architecture for FSBM video motion estimation. / Jiang, M.; Crookes, D.; Davidson, S. et al.
In: Electronics Letters, Vol. 42, No. 20, 28.09.2006, p. 1146-1148.

Research output: Contribution to Journal/Magazine › Journal article › peer-review

Harvard

Jiang, M, Crookes, D, Davidson, S & Turner, R 2006, 'Low-power systolic array processor architecture for FSBM video motion estimation', Electronics Letters, vol. 42, no. 20, pp. 1146-1148. https://doi.org/10.1049/el:20061972

APA

Jiang, M., Crookes, D., Davidson, S., & Turner, R. (2006). Low-power systolic array processor architecture for FSBM video motion estimation. Electronics Letters, 42(20), 1146-1148. https://doi.org/10.1049/el:20061972

Vancouver

Jiang M, Crookes D, Davidson S, Turner R. Low-power systolic array processor architecture for FSBM video motion estimation. Electronics Letters. 2006 Sept 28;42(20):1146-1148. doi: 10.1049/el:20061972

Author

Jiang, M. ; Crookes, D. ; Davidson, S. et al. / Low-power systolic array processor architecture for FSBM video motion estimation. In: Electronics Letters. 2006 ; Vol. 42, No. 20. pp. 1146-1148.

Bibtex

@article{13e8ed1cfa7844bab38de0583ee38367,
title = "Low-power systolic array processor architecture for FSBM video motion estimation",
abstract = "A novel power-efficient systolic array architecture is proposed for full search block matching (FSBM) motion estimation, where the partial distortion elimination algorithm is used to dynamically switch off the computation of eliminated partial candidate blocks. The RTL-level simulation shows that the proposed architecture can reduce the power consumption of the computation part of the algorithm to about 60% of that of the conventional 2D systolic arrays.",
keywords = "systolic array processor architecture, FSBM video motion estimation, full search block matching motion estimation, partial distortion elimination algorithm, RTL-level simulation, power consumption, 2D systolic arrays",
author = "M. Jiang and D. Crookes and S. Davidson and R. Turner",
year = "2006",
month = sep,
day = "28",
doi = "10.1049/el:20061972",
language = "English",
volume = "42",
pages = "1146--1148",
journal = "Electronics Letters",
issn = "0013-5194",
publisher = "Institution of Engineering and Technology",
number = "20",

}

RIS

TY - JOUR

T1 - Low-power systolic array processor architecture for FSBM video motion estimation

AU - Jiang, M.

AU - Crookes, D.

AU - Davidson, S.

AU - Turner, R.

PY - 2006/9/28

Y1 - 2006/9/28

N2 - A novel power-efficient systolic array architecture is proposed for full search block matching (FSBM) motion estimation, where the partial distortion elimination algorithm is used to dynamically switch off the computation of eliminated partial candidate blocks. The RTL-level simulation shows that the proposed architecture can reduce the power consumption of the computation part of the algorithm to about 60% of that of the conventional 2D systolic arrays.

AB - A novel power-efficient systolic array architecture is proposed for full search block matching (FSBM) motion estimation, where the partial distortion elimination algorithm is used to dynamically switch off the computation of eliminated partial candidate blocks. The RTL-level simulation shows that the proposed architecture can reduce the power consumption of the computation part of the algorithm to about 60% of that of the conventional 2D systolic arrays.

KW - systolic array processor architecture

KW - FSBM video motion estimation

KW - full search block matching motion estimation

KW - partial distortion elimination algorithm

KW - RTL-level simulation

KW - power consumption

KW - 2D systolic arrays

U2 - 10.1049/el:20061972

DO - 10.1049/el:20061972

M3 - Journal article

VL - 42

SP - 1146

EP - 1148

JO - Electronics Letters

JF - Electronics Letters

SN - 0013-5194

IS - 20

ER -