In a parallel multiwire structure, the exact spacing and size of the wires determine both the resistance and the distribution of the capacitance between the ground plane and the adjacent signal carrying conductors, and have a direct effect on the delay. Using closed-form equations that map the geometry to the wire parasitics and empirical switch factor based delay models that show how repeaters can be optimized to compensate for dynamic effects, we devise a method of analysis for optimizing throughput over a given metal area. This analysis is used to show that there is a clear optimum configuration for the wires which maximizes the total bandwidth. Additionally, closed form equations are derived, the roots of which give close to optimal solutions. It is shown that for wide buses, the optimal wire width and spacing are independent of the total width of the bus, allowing easy optimization of on-chip buses. Our analysis and results are valid for lossy interconnects as are typical of wires in submicron technologies.
In the deep submicrometre and nanometre feature size regimes, the bottleneck in very high performance VLSI circuits is the interconnect delay. Hence design of the on-chip interconnect network is of paramount importance. This paper presents a landmark analysis, the first of its kind in the literature, for optimising the total bandwidth under area and power constraints for on-chip buses, and derives design guidelines. RAE_import_type : Journal article RAE_uoa_type : General Engineering
