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On dynamic delay and repeater insertion in distributed capacitively coupled interconnects.

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSNChapter

Published

Standard

On dynamic delay and repeater insertion in distributed capacitively coupled interconnects. / Pamunuwa, Dinesh B.; Tenhunen, Hannu.
International Symposium on Quality Electronic Design, 2002. Proceedings.. IEEE, 2002. p. 240-245.

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSNChapter

Harvard

Pamunuwa, DB & Tenhunen, H 2002, On dynamic delay and repeater insertion in distributed capacitively coupled interconnects. in International Symposium on Quality Electronic Design, 2002. Proceedings.. IEEE, pp. 240-245. <http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=996740>

APA

Pamunuwa, D. B., & Tenhunen, H. (2002). On dynamic delay and repeater insertion in distributed capacitively coupled interconnects. In International Symposium on Quality Electronic Design, 2002. Proceedings. (pp. 240-245). IEEE. http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=996740

Vancouver

Pamunuwa DB, Tenhunen H. On dynamic delay and repeater insertion in distributed capacitively coupled interconnects. In International Symposium on Quality Electronic Design, 2002. Proceedings.. IEEE. 2002. p. 240-245

Author

Pamunuwa, Dinesh B. ; Tenhunen, Hannu. / On dynamic delay and repeater insertion in distributed capacitively coupled interconnects. International Symposium on Quality Electronic Design, 2002. Proceedings.. IEEE, 2002. pp. 240-245

Bibtex

@inbook{b0e24bf1be9c46bfab613bd1e9db6e42,
title = "On dynamic delay and repeater insertion in distributed capacitively coupled interconnects.",
abstract = "Repeater insertion is a well established technique to minimise the propagation delay over long resistive interconnects. In deep sub-micron technologies, as the wires are spaced ever closer and signal rise and fall times go into the sub-nanosecond region, increased crosstalk has implications for the data throughput and signal integrity. Depending on the data correlation on the coupled lines, the delay can either decrease or increase. We show that in uniform coupled lines, the response for several important switching patterns has a dominant pole characteristic. The effect of repeater insertion including optimal repeater insertion for minimising delay with worst-case cross-talk, and area constrained optimisation is considered. All equations are checked against a dynamic circuit simulator (SPECTRE).",
author = "Pamunuwa, {Dinesh B.} and Hannu Tenhunen",
note = "{"}{\textcopyright}2002 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.{"} {"}This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.{"}",
year = "2002",
language = "English",
isbn = "0-7695-1561-4",
pages = "240--245",
booktitle = "International Symposium on Quality Electronic Design, 2002. Proceedings.",
publisher = "IEEE",

}

RIS

TY - CHAP

T1 - On dynamic delay and repeater insertion in distributed capacitively coupled interconnects.

AU - Pamunuwa, Dinesh B.

AU - Tenhunen, Hannu

N1 - "©2002 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE." "This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder."

PY - 2002

Y1 - 2002

N2 - Repeater insertion is a well established technique to minimise the propagation delay over long resistive interconnects. In deep sub-micron technologies, as the wires are spaced ever closer and signal rise and fall times go into the sub-nanosecond region, increased crosstalk has implications for the data throughput and signal integrity. Depending on the data correlation on the coupled lines, the delay can either decrease or increase. We show that in uniform coupled lines, the response for several important switching patterns has a dominant pole characteristic. The effect of repeater insertion including optimal repeater insertion for minimising delay with worst-case cross-talk, and area constrained optimisation is considered. All equations are checked against a dynamic circuit simulator (SPECTRE).

AB - Repeater insertion is a well established technique to minimise the propagation delay over long resistive interconnects. In deep sub-micron technologies, as the wires are spaced ever closer and signal rise and fall times go into the sub-nanosecond region, increased crosstalk has implications for the data throughput and signal integrity. Depending on the data correlation on the coupled lines, the delay can either decrease or increase. We show that in uniform coupled lines, the response for several important switching patterns has a dominant pole characteristic. The effect of repeater insertion including optimal repeater insertion for minimising delay with worst-case cross-talk, and area constrained optimisation is considered. All equations are checked against a dynamic circuit simulator (SPECTRE).

M3 - Chapter

SN - 0-7695-1561-4

SP - 240

EP - 245

BT - International Symposium on Quality Electronic Design, 2002. Proceedings.

PB - IEEE

ER -