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SuperCache: A mechanism to minimize the front end latency

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSNConference contribution/Paperpeer-review

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SuperCache: A mechanism to minimize the front end latency. / Allan, Zhang; Helal, Sumi.
Information Technology, 2007. ITNG '07. Fourth International Conference on. IEEE, 2007. p. 908-914.

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSNConference contribution/Paperpeer-review

Harvard

Allan, Z & Helal, S 2007, SuperCache: A mechanism to minimize the front end latency. in Information Technology, 2007. ITNG '07. Fourth International Conference on. IEEE, pp. 908-914. https://doi.org/10.1109/ITNG.2007.189

APA

Allan, Z., & Helal, S. (2007). SuperCache: A mechanism to minimize the front end latency. In Information Technology, 2007. ITNG '07. Fourth International Conference on (pp. 908-914). IEEE. https://doi.org/10.1109/ITNG.2007.189

Vancouver

Allan Z, Helal S. SuperCache: A mechanism to minimize the front end latency. In Information Technology, 2007. ITNG '07. Fourth International Conference on. IEEE. 2007. p. 908-914 doi: 10.1109/ITNG.2007.189

Author

Allan, Zhang ; Helal, Sumi. / SuperCache : A mechanism to minimize the front end latency. Information Technology, 2007. ITNG '07. Fourth International Conference on. IEEE, 2007. pp. 908-914

Bibtex

@inproceedings{441e4804af6a4ba59f359d6893c564bb,
title = "SuperCache: A mechanism to minimize the front end latency",
abstract = "Modern CPU's pipeline stages can be roughly classified as front end and back end stages. Front end supplies ready (decoded, renamed) instructions and dispatches them to reservation stations where back end issues, executes and retires them. The lengthy front end stages, including instruction fetching, decoding, renaming and dispatching, play a key role in overall performance: only adequate ready instruction supply can make room for back end stages to fully exploit instruction level parallelism (ILP). The front end latency reduction is especially critical for recent deeply pipelined architecture where the front end is especially long: instruction cache access may take more than one cycle even for cache hit, let alone cache miss. In case of branch mis-prediction, the supply/demand equilibrium between front end and back end is suddenly disrupted, back end often under-utilizes available resources during the long waiting period until front end can supply new branch of instructions ready in reservation stations. In this paper, we introduce and evaluate a new mechanism (called SuperCache) that aims to reduce the front end latency by enhancing the traditional reservation pool to a SuperCache and recycle retired reservation stations. With the employment of the proposed mechanism, we can see a significant performance improvement by up to 15% even 30% in our simulations. {\textcopyright} 2007 IEEE.",
keywords = "Front end, Instruction level parallelism, Latency reduction, Pipeline, Superscalar, Classification (of information), Computer simulation, Decoding, Instruction level parallelism (ILP), Buffer storage",
author = "Zhang Allan and Sumi Helal",
year = "2007",
doi = "10.1109/ITNG.2007.189",
language = "English",
isbn = "0769527760",
pages = "908--914",
booktitle = "Information Technology, 2007. ITNG '07. Fourth International Conference on",
publisher = "IEEE",

}

RIS

TY - GEN

T1 - SuperCache

T2 - A mechanism to minimize the front end latency

AU - Allan, Zhang

AU - Helal, Sumi

PY - 2007

Y1 - 2007

N2 - Modern CPU's pipeline stages can be roughly classified as front end and back end stages. Front end supplies ready (decoded, renamed) instructions and dispatches them to reservation stations where back end issues, executes and retires them. The lengthy front end stages, including instruction fetching, decoding, renaming and dispatching, play a key role in overall performance: only adequate ready instruction supply can make room for back end stages to fully exploit instruction level parallelism (ILP). The front end latency reduction is especially critical for recent deeply pipelined architecture where the front end is especially long: instruction cache access may take more than one cycle even for cache hit, let alone cache miss. In case of branch mis-prediction, the supply/demand equilibrium between front end and back end is suddenly disrupted, back end often under-utilizes available resources during the long waiting period until front end can supply new branch of instructions ready in reservation stations. In this paper, we introduce and evaluate a new mechanism (called SuperCache) that aims to reduce the front end latency by enhancing the traditional reservation pool to a SuperCache and recycle retired reservation stations. With the employment of the proposed mechanism, we can see a significant performance improvement by up to 15% even 30% in our simulations. © 2007 IEEE.

AB - Modern CPU's pipeline stages can be roughly classified as front end and back end stages. Front end supplies ready (decoded, renamed) instructions and dispatches them to reservation stations where back end issues, executes and retires them. The lengthy front end stages, including instruction fetching, decoding, renaming and dispatching, play a key role in overall performance: only adequate ready instruction supply can make room for back end stages to fully exploit instruction level parallelism (ILP). The front end latency reduction is especially critical for recent deeply pipelined architecture where the front end is especially long: instruction cache access may take more than one cycle even for cache hit, let alone cache miss. In case of branch mis-prediction, the supply/demand equilibrium between front end and back end is suddenly disrupted, back end often under-utilizes available resources during the long waiting period until front end can supply new branch of instructions ready in reservation stations. In this paper, we introduce and evaluate a new mechanism (called SuperCache) that aims to reduce the front end latency by enhancing the traditional reservation pool to a SuperCache and recycle retired reservation stations. With the employment of the proposed mechanism, we can see a significant performance improvement by up to 15% even 30% in our simulations. © 2007 IEEE.

KW - Front end

KW - Instruction level parallelism

KW - Latency reduction

KW - Pipeline

KW - Superscalar

KW - Classification (of information)

KW - Computer simulation

KW - Decoding

KW - Instruction level parallelism (ILP)

KW - Buffer storage

U2 - 10.1109/ITNG.2007.189

DO - 10.1109/ITNG.2007.189

M3 - Conference contribution/Paper

SN - 0769527760

SP - 908

EP - 914

BT - Information Technology, 2007. ITNG '07. Fourth International Conference on

PB - IEEE

ER -