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System in Package Technology - Design for Manufacture Challenges.

Research output: Contribution to Journal/MagazineJournal articlepeer-review

<mark>Journal publication date</mark>1/02/2007
<mark>Journal</mark>Circuit World
Issue number1
Number of pages11
Pages (from-to)36-46
Publication StatusPublished
<mark>Original language</mark>English


Purpose – To present key challenges associated with the evolution of system-in-package technologies and present technical work in reliability modeling and embedded test that contributes to these challenges. Design/methodology/approach – Key challenges have been identified from the electronics and integrated MEMS industrial sectors. Solutions to optimising the reliability of a typical assembly process and reducing the cost of production test have been studied through simulation and modelling studies based on technology data released by NXP and in collaboration with EDA tool vendors Coventor and Flomerics. Findings – Characterised models that deliver special and material dependent reliability data that can be used to optimize robustness of SiP assemblies together with results that indicate relative contributions of various structural variables. An initial analytical model for solder ball reliability and a solution for embedding a low cost test for a capacitive RF-MEMS switch identified as an SiP component presenting a key test challenge. Research limitations/implications – Results will contribute to the further development of NXP wafer level system-in-package technology. Limitations are that feedback on the implementation of recommendations and the physical characterisation of the embedded test solution. Originality/value – Both the methodology and associated studies on the structural reliability of an industrial SiP technology are unique. The analytical model for solder ball life is new as is the embedded test solution for the RF-MEMS switch.

Bibliographic note

A compilation of results from a collaboration between my team, the University of Greenwich and NXP, Caen under the EPSRC IeMRC project ""Design for Manufacture Methodology for SiP"". The results obtained on structural reliability analysis in collaboration with the University of Greenwich are being used within NXP Semiconductors (ref. jean-marc.yannou@nxp.com) and the study on an embedded test solution for the RF-MEMS component formed the basis for a new IeMRC project with NXP and others. The work is to our knowledge the first peer reviewed article addressing solder ball reliability and embedded test on this type of SiP platform. RAE_import_type : Journal article RAE_uoa_type : General Engineering