Scanning spreading resistance microscopy (SSRM) is a powerful technique for quantitative two-and three-dimensional carrier profiling of semiconductor devices with sub-nm spatial resolution. However, considering the sub-10 nm dimensions of advanced devices and the introduction of three-dimensional architectures like fin field effect transistor (FinFET) and nanowires, the measured spreading resistance is easily impacted by parasitic series resistances present in the system. The limited amount of material, the presence of multiple interfaces, and confined current paths may increase the total resistance measured by SSRM beyond the expected spreading resistance, which can ultimately lead to an inaccurate carrier quantification. Here, we report a simulation assisted experimental study to identify the different parameters affecting the SSRM measurements in confined volumes. Experimentally, the two-dimensional current confinement is obtained by progressively thinning down uniformly doped blanket silicon on insulator wafers using scalpel SSRM. The concomitant SSRM provides detailed electrical information as a function of depth up to oxide interface. We show that the resistance is most affected by the interface traps in case of a heterogeneous sample, followed by the intrinsic resistance of the current carrying paths. Furthermore, we show that accurate carrier quantification is ensured for typical back contact distances of 1 μm if the region of interest is at least nine times larger than the probe radius. © 2020 Author(s).