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Design-for-test structure to facilitate test vector application with low performance loss in non-test mode.

Research output: Contribution to journalJournal article

Published

Journal publication date1993
JournalIEE Electronics Letters
Journal number16
Volume29
Number of pages3
Pages1438-1440
Original languageEnglish

Abstract

A switching based circuit is described which allows application of voltage test vectors to internal nodes of a chip without the problem of backdriving. The new circuit has low impact on the performance of an analogue circuit in terms of loss of bandwidth and allows simple application of analogue test voltages into internal nodes. The circuit described facilitates implementation of the forthcoming IEEE 1149.4 DfT philosophy [1].

Bibliographic note

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