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Design-for-test structure to facilitate test vector application with low performance loss in non-test mode.

Research output: Contribution to journalJournal article

<mark>Journal publication date</mark>1993
<mark>Journal</mark>Electronics Letters
Issue number16
Number of pages3
Pages (from-to)1438-1440
Publication StatusPublished
<mark>Original language</mark>English


A switching based circuit is described which allows application of voltage test vectors to internal nodes of a chip without the problem of backdriving. The new circuit has low impact on the performance of an analogue circuit in terms of loss of bandwidth and allows simple application of analogue test voltages into internal nodes. The circuit described facilitates implementation of the forthcoming IEEE 1149.4 DfT philosophy [1].

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