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Design-for-test structure to facilitate test vector application with low performance loss in non-test mode.

Research output: Contribution to Journal/Magazine › Journal article

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Design-for-test structure to facilitate test vector application with low performance loss in non-test mode. / Bratt, Adrian; Harvey, R. J. A.; Dorey, A. P. et al.
In: Electronics Letters, Vol. 29, No. 16, 1993, p. 1438-1440.

Research output: Contribution to Journal/Magazine › Journal article

Harvard

Bratt, A, Harvey, RJA, Dorey, AP & Richardson, AMD 1993, 'Design-for-test structure to facilitate test vector application with low performance loss in non-test mode.', Electronics Letters, vol. 29, no. 16, pp. 1438-1440. https://doi.org/10.1049/el:19930963

APA

Bratt, A., Harvey, R. J. A., Dorey, A. P., & Richardson, A. M. D. (1993). Design-for-test structure to facilitate test vector application with low performance loss in non-test mode. Electronics Letters, 29(16), 1438-1440. https://doi.org/10.1049/el:19930963

Vancouver

Bratt A, Harvey RJA, Dorey AP, Richardson AMD. Design-for-test structure to facilitate test vector application with low performance loss in non-test mode. Electronics Letters. 1993;29(16):1438-1440. doi: 10.1049/el:19930963

Author

Bratt, Adrian ; Harvey, R. J. A. ; Dorey, A. P. et al. / Design-for-test structure to facilitate test vector application with low performance loss in non-test mode. In: Electronics Letters. 1993 ; Vol. 29, No. 16. pp. 1438-1440.

Bibtex

@article{ced67055a3c749eeba0f0df7019c3eef,
title = "Design-for-test structure to facilitate test vector application with low performance loss in non-test mode.",
abstract = "A switching based circuit is described which allows application of voltage test vectors to internal nodes of a chip without the problem of backdriving. The new circuit has low impact on the performance of an analogue circuit in terms of loss of bandwidth and allows simple application of analogue test voltages into internal nodes. The circuit described facilitates implementation of the forthcoming IEEE 1149.4 DfT philosophy [1].",
author = "Adrian Bratt and Harvey, {R. J. A.} and Dorey, {A. P.} and Richardson, {A. M. D.}",
note = "{"}{\textcopyright}1993 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.{"} {"}This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.{"}",
year = "1993",
doi = "10.1049/el:19930963",
language = "English",
volume = "29",
pages = "1438--1440",
journal = "Electronics Letters",
issn = "1350-911X",
publisher = "Institution of Engineering and Technology",
number = "16",

}

RIS

TY - JOUR

T1 - Design-for-test structure to facilitate test vector application with low performance loss in non-test mode.

AU - Bratt, Adrian

AU - Harvey, R. J. A.

AU - Dorey, A. P.

AU - Richardson, A. M. D.

N1 - "©1993 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE." "This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder."

PY - 1993

Y1 - 1993

N2 - A switching based circuit is described which allows application of voltage test vectors to internal nodes of a chip without the problem of backdriving. The new circuit has low impact on the performance of an analogue circuit in terms of loss of bandwidth and allows simple application of analogue test voltages into internal nodes. The circuit described facilitates implementation of the forthcoming IEEE 1149.4 DfT philosophy [1].

AB - A switching based circuit is described which allows application of voltage test vectors to internal nodes of a chip without the problem of backdriving. The new circuit has low impact on the performance of an analogue circuit in terms of loss of bandwidth and allows simple application of analogue test voltages into internal nodes. The circuit described facilitates implementation of the forthcoming IEEE 1149.4 DfT philosophy [1].

U2 - 10.1049/el:19930963

DO - 10.1049/el:19930963

M3 - Journal article

VL - 29

SP - 1438

EP - 1440

JO - Electronics Letters

JF - Electronics Letters

SN - 1350-911X

IS - 16

ER -