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A design for testability study on a high performance automatic gain control circuit.

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Publication date1998
Host publicationProceedings of the 16th IEEE VLSI test symposium
Number of pages10
<mark>Original language</mark>English


A comprehensive testability study on a commercial automatic gain control circuit is presented which aims to identify design for testability (DfT) modifications to both reduce production test cost and improve test quality. A fault simulation strategy based on layout extracted faults has been used to support the study. The paper proposes a number of DfT modifications at the layout, schematic and system levels together with testability. Guidelines that may well have generic applicability. Proposals for using the modifications to achieve partial self test are made and estimates of achieved fault coverage and quality levels presented

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