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A design for testability study on a high performance automatic gain control circuit.

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A design for testability study on a high performance automatic gain control circuit. / Lechner, A.; Richardson, A. M. D.; Hermes, B. et al.
Proceedings of the 16th IEEE VLSI test symposium. IEEE, 1998. p. 376-385.

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

Harvard

Lechner, A, Richardson, AMD, Hermes, B & Ohletz, M 1998, A design for testability study on a high performance automatic gain control circuit. in Proceedings of the 16th IEEE VLSI test symposium. IEEE, pp. 376-385. https://doi.org/10.1109/VTEST.1998.670893

APA

Lechner, A., Richardson, A. M. D., Hermes, B., & Ohletz, M. (1998). A design for testability study on a high performance automatic gain control circuit. In Proceedings of the 16th IEEE VLSI test symposium (pp. 376-385). IEEE. https://doi.org/10.1109/VTEST.1998.670893

Vancouver

Lechner A, Richardson AMD, Hermes B, Ohletz M. A design for testability study on a high performance automatic gain control circuit. In Proceedings of the 16th IEEE VLSI test symposium. IEEE. 1998. p. 376-385 doi: 10.1109/VTEST.1998.670893

Author

Lechner, A. ; Richardson, A. M. D. ; Hermes, B. et al. / A design for testability study on a high performance automatic gain control circuit. Proceedings of the 16th IEEE VLSI test symposium. IEEE, 1998. pp. 376-385

Bibtex

@inbook{aca31ed081f0413db21f9330c7e4c914,
title = "A design for testability study on a high performance automatic gain control circuit.",
abstract = "A comprehensive testability study on a commercial automatic gain control circuit is presented which aims to identify design for testability (DfT) modifications to both reduce production test cost and improve test quality. A fault simulation strategy based on layout extracted faults has been used to support the study. The paper proposes a number of DfT modifications at the layout, schematic and system levels together with testability. Guidelines that may well have generic applicability. Proposals for using the modifications to achieve partial self test are made and estimates of achieved fault coverage and quality levels presented",
author = "A. Lechner and Richardson, {A. M. D.} and B. Hermes and M. Ohletz",
note = "{"}{\textcopyright}1998 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.{"} {"}This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.{"}",
year = "1998",
doi = "10.1109/VTEST.1998.670893",
language = "English",
pages = "376--385",
booktitle = "Proceedings of the 16th IEEE VLSI test symposium",
publisher = "IEEE",

}

RIS

TY - CHAP

T1 - A design for testability study on a high performance automatic gain control circuit.

AU - Lechner, A.

AU - Richardson, A. M. D.

AU - Hermes, B.

AU - Ohletz, M.

N1 - "©1998 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE." "This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder."

PY - 1998

Y1 - 1998

N2 - A comprehensive testability study on a commercial automatic gain control circuit is presented which aims to identify design for testability (DfT) modifications to both reduce production test cost and improve test quality. A fault simulation strategy based on layout extracted faults has been used to support the study. The paper proposes a number of DfT modifications at the layout, schematic and system levels together with testability. Guidelines that may well have generic applicability. Proposals for using the modifications to achieve partial self test are made and estimates of achieved fault coverage and quality levels presented

AB - A comprehensive testability study on a commercial automatic gain control circuit is presented which aims to identify design for testability (DfT) modifications to both reduce production test cost and improve test quality. A fault simulation strategy based on layout extracted faults has been used to support the study. The paper proposes a number of DfT modifications at the layout, schematic and system levels together with testability. Guidelines that may well have generic applicability. Proposals for using the modifications to achieve partial self test are made and estimates of achieved fault coverage and quality levels presented

U2 - 10.1109/VTEST.1998.670893

DO - 10.1109/VTEST.1998.670893

M3 - Chapter

SP - 376

EP - 385

BT - Proceedings of the 16th IEEE VLSI test symposium

PB - IEEE

ER -