Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Conference contribution/Paper › peer-review
Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Conference contribution/Paper › peer-review
}
TY - GEN
T1 - A digital partial built-in self-test structure for a high performance automatic gain control circuit
AU - Lechner, A
AU - Ferguson, J
AU - Richardson, A
AU - Hermes, B
PY - 1999
Y1 - 1999
N2 - It is now widely recognised that Design-for-Testability and Built-in Self-Test techniques rc ill be mandatory to meet test and quality specifications in next generation mired signal integrated systems. This paper describes a new digital on-chip post processing function capable of reducing production test time for a high performance automatic gain control circuit by 70%.
AB - It is now widely recognised that Design-for-Testability and Built-in Self-Test techniques rc ill be mandatory to meet test and quality specifications in next generation mired signal integrated systems. This paper describes a new digital on-chip post processing function capable of reducing production test time for a high performance automatic gain control circuit by 70%.
KW - DESIGN-FOR-TEST
KW - ANALOG
KW - BIST
KW - DAC
KW - ADC
U2 - 10.1109/DATE.1999.761127
DO - 10.1109/DATE.1999.761127
M3 - Conference contribution/Paper
SN - 0-7695-0078-1
SP - 232
EP - 238
BT - DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION 1999, PROCEEDINGS
A2 - Borrione, D
A2 - Ernst, R
PB - IEEE COMPUTER SOC
CY - LOS ALAMITOS
ER -