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A low-power high-radix serial-parallel multiplier

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Publication date2007
Host publication2007 Conference on Circuit Theory and Design 
Number of pages4
ISBN (Print)9781424413416
<mark>Original language</mark>English


In this paper, we introduce a novel high-radix binary signed digit (BSD) serial-parallel multiplier suitable for low-power high-speed multiplication. The proposed N- bittimesN-bit radix-16 serial-parallel multiplier can reduce the number of accumulation cycles of partial products to as much as N/4, and eliminate most of the invertion operations which consume power in a conventional multiplier in generating the partial products. Unlike other high-radix methods, the pre-multiplication in the new algorithm employs a BSD method which requires no extra adder, and thus removes the extra delay for additions which hinders other high-radix algorithms.