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A low-power high-radix serial-parallel multiplier

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A low-power high-radix serial-parallel multiplier. / Crookes, Danny; Jiang, Richard M.
2007 Conference on Circuit Theory and Design . Vol. 1-3 IEEE, 2007. p. 460-463.

Research output: Contribution in Book/Report/Proceedings - With ISBN/ISSN › Chapter

Harvard

Crookes, D & Jiang, RM 2007, A low-power high-radix serial-parallel multiplier. in 2007 Conference on Circuit Theory and Design . vol. 1-3, IEEE, pp. 460-463. https://doi.org/10.1109/ECCTD.2007.4529632

APA

Crookes, D., & Jiang, R. M. (2007). A low-power high-radix serial-parallel multiplier. In 2007 Conference on Circuit Theory and Design  (Vol. 1-3, pp. 460-463). IEEE. https://doi.org/10.1109/ECCTD.2007.4529632

Vancouver

Crookes D, Jiang RM. A low-power high-radix serial-parallel multiplier. In 2007 Conference on Circuit Theory and Design . Vol. 1-3. IEEE. 2007. p. 460-463 doi: 10.1109/ECCTD.2007.4529632

Author

Crookes, Danny ; Jiang, Richard M. / A low-power high-radix serial-parallel multiplier. 2007 Conference on Circuit Theory and Design . Vol. 1-3 IEEE, 2007. pp. 460-463

Bibtex

@inbook{eae776c6a42740e9823d8c587b2aa5ee,
title = "A low-power high-radix serial-parallel multiplier",
abstract = "In this paper, we introduce a novel high-radix binary signed digit (BSD) serial-parallel multiplier suitable for low-power high-speed multiplication. The proposed N- bittimesN-bit radix-16 serial-parallel multiplier can reduce the number of accumulation cycles of partial products to as much as N/4, and eliminate most of the invertion operations which consume power in a conventional multiplier in generating the partial products. Unlike other high-radix methods, the pre-multiplication in the new algorithm employs a BSD method which requires no extra adder, and thus removes the extra delay for additions which hinders other high-radix algorithms.",
author = "Danny Crookes and Jiang, {Richard M.}",
year = "2007",
doi = "10.1109/ECCTD.2007.4529632",
language = "English",
isbn = "9781424413416",
volume = "1-3",
pages = "460--463",
booktitle = "2007 Conference on Circuit Theory and Design ",
publisher = "IEEE",

}

RIS

TY - CHAP

T1 - A low-power high-radix serial-parallel multiplier

AU - Crookes, Danny

AU - Jiang, Richard M.

PY - 2007

Y1 - 2007

N2 - In this paper, we introduce a novel high-radix binary signed digit (BSD) serial-parallel multiplier suitable for low-power high-speed multiplication. The proposed N- bittimesN-bit radix-16 serial-parallel multiplier can reduce the number of accumulation cycles of partial products to as much as N/4, and eliminate most of the invertion operations which consume power in a conventional multiplier in generating the partial products. Unlike other high-radix methods, the pre-multiplication in the new algorithm employs a BSD method which requires no extra adder, and thus removes the extra delay for additions which hinders other high-radix algorithms.

AB - In this paper, we introduce a novel high-radix binary signed digit (BSD) serial-parallel multiplier suitable for low-power high-speed multiplication. The proposed N- bittimesN-bit radix-16 serial-parallel multiplier can reduce the number of accumulation cycles of partial products to as much as N/4, and eliminate most of the invertion operations which consume power in a conventional multiplier in generating the partial products. Unlike other high-radix methods, the pre-multiplication in the new algorithm employs a BSD method which requires no extra adder, and thus removes the extra delay for additions which hinders other high-radix algorithms.

U2 - 10.1109/ECCTD.2007.4529632

DO - 10.1109/ECCTD.2007.4529632

M3 - Chapter

SN - 9781424413416

VL - 1-3

SP - 460

EP - 463

BT - 2007 Conference on Circuit Theory and Design 

PB - IEEE

ER -