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A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime.

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<mark>Journal publication date</mark>1/10/2004
<mark>Journal</mark>Integration, the VLSI Journal
Issue number1
Volume38
Number of pages15
Pages (from-to)3-17
Publication StatusPublished
<mark>Original language</mark>English

Abstract

On-chip packet-switched networks have been proposed for future giga-scale integration in the nano-metre regime. This paper examines likely architectures for such networks and considers trade-offs in the layout, performance, and power consumption based on full-swing, voltage-mode CMOS signalling. A study is carried out for a future technology with parameters as predicted by the International Technology Roadmap for Semiconductors to yield a quantitative comparison of the performance and power trade-off for the network. Important physical level issues are discussed.

Bibliographic note

One of the most promising architectures for trillion device electronic systems is the Network-On-Chip architecture. Although many other papers described high-level protocols and architectural issues, this paper was the first in the literature to address the performance of the on-chip network, under the physical constraints of interconnections in the deep sub micrometer regime. This paper derives critical cost and performance metrics and shows the role of the network bandwidth in dictating system perfomance. RAE_import_type : Journal article RAE_uoa_type : General Engineering