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A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime.

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A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime. / Pamunuwa, Dinesh B.; Öberg, Johnny; Millberg, Mikael et al.
In: Integration, the VLSI Journal, Vol. 38, No. 1, 01.10.2004, p. 3-17.

Research output: Contribution to Journal/Magazine › Journal article › peer-review

Harvard

Pamunuwa, DB, Öberg, J, Millberg, M, Zheng, L-R, Jantsch, A & Tenhunen, H 2004, 'A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime.', Integration, the VLSI Journal, vol. 38, no. 1, pp. 3-17. https://doi.org/10.1016/j.vlsi.2004.03.005

APA

Pamunuwa, D. B., Öberg, J., Millberg, M., Zheng, L.-R., Jantsch, A., & Tenhunen, H. (2004). A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime. Integration, the VLSI Journal, 38(1), 3-17. https://doi.org/10.1016/j.vlsi.2004.03.005

Vancouver

Pamunuwa DB, Öberg J, Millberg M, Zheng LR, Jantsch A, Tenhunen H. A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime. Integration, the VLSI Journal. 2004 Oct 1;38(1):3-17. doi: 10.1016/j.vlsi.2004.03.005

Author

Pamunuwa, Dinesh B. ; Öberg, Johnny ; Millberg, Mikael et al. / A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime. In: Integration, the VLSI Journal. 2004 ; Vol. 38, No. 1. pp. 3-17.

Bibtex

@article{bf52bb7fa8cc4eac8a303501365ed137,
title = "A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime.",
abstract = "On-chip packet-switched networks have been proposed for future giga-scale integration in the nano-metre regime. This paper examines likely architectures for such networks and considers trade-offs in the layout, performance, and power consumption based on full-swing, voltage-mode CMOS signalling. A study is carried out for a future technology with parameters as predicted by the International Technology Roadmap for Semiconductors to yield a quantitative comparison of the performance and power trade-off for the network. Important physical level issues are discussed.",
author = "Pamunuwa, {Dinesh B.} and Johnny {\"O}berg and Mikael Millberg and Li-Rong Zheng and Axel Jantsch and Hannu Tenhunen",
note = "One of the most promising architectures for trillion device electronic systems is the Network-On-Chip architecture. Although many other papers described high-level protocols and architectural issues, this paper was the first in the literature to address the performance of the on-chip network, under the physical constraints of interconnections in the deep sub micrometer regime. This paper derives critical cost and performance metrics and shows the role of the network bandwidth in dictating system perfomance. RAE_import_type : Journal article RAE_uoa_type : General Engineering",
year = "2004",
month = oct,
day = "1",
doi = "10.1016/j.vlsi.2004.03.005",
language = "English",
volume = "38",
pages = "3--17",
journal = "Integration, the VLSI Journal",
issn = "0167-9260",
publisher = "Elsevier",
number = "1",

}

RIS

TY - JOUR

T1 - A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime.

AU - Pamunuwa, Dinesh B.

AU - Öberg, Johnny

AU - Millberg, Mikael

AU - Zheng, Li-Rong

AU - Jantsch, Axel

AU - Tenhunen, Hannu

N1 - One of the most promising architectures for trillion device electronic systems is the Network-On-Chip architecture. Although many other papers described high-level protocols and architectural issues, this paper was the first in the literature to address the performance of the on-chip network, under the physical constraints of interconnections in the deep sub micrometer regime. This paper derives critical cost and performance metrics and shows the role of the network bandwidth in dictating system perfomance. RAE_import_type : Journal article RAE_uoa_type : General Engineering

PY - 2004/10/1

Y1 - 2004/10/1

N2 - On-chip packet-switched networks have been proposed for future giga-scale integration in the nano-metre regime. This paper examines likely architectures for such networks and considers trade-offs in the layout, performance, and power consumption based on full-swing, voltage-mode CMOS signalling. A study is carried out for a future technology with parameters as predicted by the International Technology Roadmap for Semiconductors to yield a quantitative comparison of the performance and power trade-off for the network. Important physical level issues are discussed.

AB - On-chip packet-switched networks have been proposed for future giga-scale integration in the nano-metre regime. This paper examines likely architectures for such networks and considers trade-offs in the layout, performance, and power consumption based on full-swing, voltage-mode CMOS signalling. A study is carried out for a future technology with parameters as predicted by the International Technology Roadmap for Semiconductors to yield a quantitative comparison of the performance and power trade-off for the network. Important physical level issues are discussed.

U2 - 10.1016/j.vlsi.2004.03.005

DO - 10.1016/j.vlsi.2004.03.005

M3 - Journal article

VL - 38

SP - 3

EP - 17

JO - Integration, the VLSI Journal

JF - Integration, the VLSI Journal

SN - 0167-9260

IS - 1

ER -