Research output: Contribution to Journal/Magazine › Journal article › peer-review
Research output: Contribution to Journal/Magazine › Journal article › peer-review
}
TY - JOUR
T1 - An area-efficient FFT architecture for OFDM digital video broadcasting
AU - Jiang, Richard M.
PY - 2007/11/1
Y1 - 2007/11/1
N2 - In this paper, a novel high-performance 8k-point fast Fourier transform(DFT) processor architecture for OFDM digital video broadcasting(DVB) is proposed based on a novel radix-8 FFT architecture. Distributed arithmetic(DA) is used to implement the basic 8-point FFTs directly, where the hardware cost of complex multipliers and adders can be greatly reduced. The twiddle multiplications are performed by CORDIC-based twiddle multipliers. The results show that the proposed processor architecture can greatly save the area cost while keeping a high-speed processing speed, which may be attractive for many real-time DVB-T systems.
AB - In this paper, a novel high-performance 8k-point fast Fourier transform(DFT) processor architecture for OFDM digital video broadcasting(DVB) is proposed based on a novel radix-8 FFT architecture. Distributed arithmetic(DA) is used to implement the basic 8-point FFTs directly, where the hardware cost of complex multipliers and adders can be greatly reduced. The twiddle multiplications are performed by CORDIC-based twiddle multipliers. The results show that the proposed processor architecture can greatly save the area cost while keeping a high-speed processing speed, which may be attractive for many real-time DVB-T systems.
KW - DVB-T
KW - FFT
KW - HDTV
KW - OFDM demodulation
U2 - 10.1109/TCE.2007.4429219
DO - 10.1109/TCE.2007.4429219
M3 - Journal article
AN - SCOPUS:39549090468
VL - 53
SP - 1322
EP - 1326
JO - IEEE Transactions on Consumer Electronics
JF - IEEE Transactions on Consumer Electronics
SN - 0098-3063
IS - 4
ER -