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An area-efficient FFT architecture for OFDM digital video broadcasting

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An area-efficient FFT architecture for OFDM digital video broadcasting. / Jiang, Richard M.
In: IEEE Transactions on Consumer Electronics, Vol. 53, No. 4, 01.11.2007, p. 1322-1326.

Research output: Contribution to Journal/MagazineJournal articlepeer-review

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Jiang, RM 2007, 'An area-efficient FFT architecture for OFDM digital video broadcasting', IEEE Transactions on Consumer Electronics, vol. 53, no. 4, pp. 1322-1326. https://doi.org/10.1109/TCE.2007.4429219

APA

Vancouver

Jiang RM. An area-efficient FFT architecture for OFDM digital video broadcasting. IEEE Transactions on Consumer Electronics. 2007 Nov 1;53(4):1322-1326. doi: 10.1109/TCE.2007.4429219

Author

Jiang, Richard M. / An area-efficient FFT architecture for OFDM digital video broadcasting. In: IEEE Transactions on Consumer Electronics. 2007 ; Vol. 53, No. 4. pp. 1322-1326.

Bibtex

@article{facce90bd470491da21cb740c10bfb2a,
title = "An area-efficient FFT architecture for OFDM digital video broadcasting",
abstract = "In this paper, a novel high-performance 8k-point fast Fourier transform(DFT) processor architecture for OFDM digital video broadcasting(DVB) is proposed based on a novel radix-8 FFT architecture. Distributed arithmetic(DA) is used to implement the basic 8-point FFTs directly, where the hardware cost of complex multipliers and adders can be greatly reduced. The twiddle multiplications are performed by CORDIC-based twiddle multipliers. The results show that the proposed processor architecture can greatly save the area cost while keeping a high-speed processing speed, which may be attractive for many real-time DVB-T systems.",
keywords = "DVB-T, FFT, HDTV, OFDM demodulation",
author = "Jiang, {Richard M.}",
year = "2007",
month = nov,
day = "1",
doi = "10.1109/TCE.2007.4429219",
language = "English",
volume = "53",
pages = "1322--1326",
journal = "IEEE Transactions on Consumer Electronics",
issn = "0098-3063",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "4",

}

RIS

TY - JOUR

T1 - An area-efficient FFT architecture for OFDM digital video broadcasting

AU - Jiang, Richard M.

PY - 2007/11/1

Y1 - 2007/11/1

N2 - In this paper, a novel high-performance 8k-point fast Fourier transform(DFT) processor architecture for OFDM digital video broadcasting(DVB) is proposed based on a novel radix-8 FFT architecture. Distributed arithmetic(DA) is used to implement the basic 8-point FFTs directly, where the hardware cost of complex multipliers and adders can be greatly reduced. The twiddle multiplications are performed by CORDIC-based twiddle multipliers. The results show that the proposed processor architecture can greatly save the area cost while keeping a high-speed processing speed, which may be attractive for many real-time DVB-T systems.

AB - In this paper, a novel high-performance 8k-point fast Fourier transform(DFT) processor architecture for OFDM digital video broadcasting(DVB) is proposed based on a novel radix-8 FFT architecture. Distributed arithmetic(DA) is used to implement the basic 8-point FFTs directly, where the hardware cost of complex multipliers and adders can be greatly reduced. The twiddle multiplications are performed by CORDIC-based twiddle multipliers. The results show that the proposed processor architecture can greatly save the area cost while keeping a high-speed processing speed, which may be attractive for many real-time DVB-T systems.

KW - DVB-T

KW - FFT

KW - HDTV

KW - OFDM demodulation

U2 - 10.1109/TCE.2007.4429219

DO - 10.1109/TCE.2007.4429219

M3 - Journal article

AN - SCOPUS:39549090468

VL - 53

SP - 1322

EP - 1326

JO - IEEE Transactions on Consumer Electronics

JF - IEEE Transactions on Consumer Electronics

SN - 0098-3063

IS - 4

ER -