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Area-efficient high-speed 3D DWT processor architecture

Research output: Contribution to Journal/MagazineJournal articlepeer-review

<mark>Journal publication date</mark>26/04/2007
<mark>Journal</mark>Electronics Letters
Issue number9
Number of pages2
Pages (from-to)502-503
Publication StatusPublished
<mark>Original language</mark>English


An area-efficient high-throughput architecture based on distributed arithmetic is proposed for 3D discrete wavelet transform (DWT). The 3D DWT processor was designed in VHDL and mapped to a Xilinx Virtex-E FPGA. The processor runs up to 85 MHz, which can process the five-level DWT analysis of a 128times128times128 fMRI volume image in 20 ms